Semiconductor device and imaging unit

ABSTRACT

A semiconductor device according to an embodiment of the present disclosure has a first wiring layer and a first insulating layer stacked therein. The first wiring layer includes a plurality of first wiring lines extending in one direction. The first insulating layer is provided on the first wiring layer. The first insulating layer forms a gap at least partially between the plurality of wiring lines. The first insulating layer has, above the gap, a stack region in which a first insulating film and a second insulating film are stacked. The first insulating film and the second insulating film include materials different from each other.

TECHNICAL FIELD

The present disclosure relates, for example, to a semiconductor device that has a gap between wiring lines and an imaging unit including the semiconductor device.

BACKGROUND ART

In recent years, as finer semiconductor integrated circuit elements are made, the intervals between the elements and the intervals between wiring lines that connect the elements have been narrower in semiconductor devices. With respect to this, for example, each of PTLs 1 and 2 discloses a semiconductor device having the capacitance decreased between wiring lines by forming a gap (air gap) between the wiring lines.

CITATION LIST Patent Literature

PTL 1: Japanese Unexamined Patent Application Publication No. 2009-016790

PTL 2: Japanese Unexamined Patent Application Publication No. 2013-149679

SUMMARY OF THE INVENTION

Incidentally, a semiconductor device is requested to reduce variations in wiring capacitance.

It is desirable to provide a semiconductor device and an imaging unit each of which makes it possible to reduce variations in wiring capacitance.

A semiconductor device according to an embodiment of the present disclosure has a first wiring layer and a first insulating layer stacked therein. The first wiring layer includes a plurality of first wiring lines extending in one direction. The first insulating layer is provided on the first wiring layer. The first insulating layer forms a gap at least partially between the plurality of wiring lines. The first insulating layer has, above the gap, a stack region in which a first insulating film and a second insulating film are stacked. The first insulating film and the second insulating film include materials different from each other.

A first imaging unit according to an embodiment of the present disclosure includes: a first substrate; and a second substrate. The first substrate includes a sensor pixel on a first semiconductor substrate. The sensor pixel performs photoelectric conversion. The second substrate includes a readout circuit on a second semiconductor substrate and includes a multilayer wiring layer stacked on the second semiconductor substrate. The readout circuit outputs a pixel signal based on electric charge outputted from the sensor pixel. The second substrate is stacked on the first substrate. The multilayer wiring layer has a configuration of the semiconductor device according to the embodiment described above.

A second imaging unit according to an embodiment of the present disclosure includes: a first substrate; and a second substrate. The first substrate includes a first semiconductor substrate and a first multilayer wiring layer. The first semiconductor substrate includes a sensor pixel and a readout circuit. The sensor pixel performs photoelectric conversion. The readout circuit outputs a pixel signal based on electric charge outputted from the sensor pixel. The first multilayer wiring layer is stacked on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second multilayer wiring layer. The second semiconductor substrate includes at least one of a logic circuit or a memory circuit. The logic circuit processes the pixel signal. The memory circuit holds the pixel signal. The second multilayer wiring layer is stacked on the second semiconductor substrate. At least one of the first multilayer wiring layer or the second multilayer wiring layer has the configuration of the semiconductor device according to the embodiment described above.

The semiconductor device according to the embodiment of the present disclosure, the first imaging unit according to the embodiment, and the second imaging unit according to the embodiment are each provided with the first insulating layer above the first wiring layer. The first wiring layer including the plurality of first wiring lines extending in the one direction. The first insulating layer has the gaps formed between the plurality of wiring lines. The first insulating layer has the stack region above the gaps. The first insulating film and the second insulating film are staked in the stack region. The first insulating film and the second insulating film include materials different from each other. This reduces variations in the film thickness of the first insulating layer within the plane.

BRIEF DESCRIPTION OF DRAWING

FIG. 1 is a diagram illustrating an example of a cross-sectional configuration of a semiconductor device according to an embodiment of the present disclosure in a vertical direction.

FIG. 2 is a diagram illustrating an example of a cross-sectional configuration of a whole of the semiconductor device illustrated in FIG. 1 in a horizontal direction.

FIG. 3 is a diagram illustrating another example of a cross-sectional configuration of the semiconductor device illustrated in FIG. 1 in the vertical direction.

FIG. 4A is a diagram illustrating an example of a process of manufacturing the semiconductor device illustrated in FIG. 1.

FIG. 4B is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4A.

FIG. 4C is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4B.

FIG. 4D is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4C.

FIG. 4E is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4D.

FIG. 4F is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4E.

FIG. 4G is a diagram illustrating an example of a manufacturing process subsequent to FIG. 4F.

FIG. 5A is a diagram subsequent to FIG. 4G illustrating the example of the process of manufacturing the semiconductor device illustrated in FIG. 3.

FIG. 5B is a diagram illustrating an example of a manufacturing process subsequent to FIG. 5A.

FIG. 5C is a diagram illustrating an example of a manufacturing process subsequent to FIG. 5B.

FIG. 6 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to an embodiment of the present disclosure in the vertical direction.

FIG. 7 is a diagram illustrating an example of a schematic configuration of the imaging unit illustrated in FIG. 6.

FIG. 8 is a diagram illustrating an example of the sensor pixel and the readout circuit illustrated in FIG. 6.

FIG. 9 is a diagram illustrating an example of the sensor pixel and the readout circuit illustrated in FIG. 6.

FIG. 10 is a diagram illustrating an example of the sensor pixel and the readout circuit illustrated in FIG. 6.

FIG. 11 is a diagram illustrating an example of the sensor pixel and the readout circuit illustrated in FIG. 6.

FIG. 12 is a diagram illustrating an example of a coupling mode between a plurality of readout circuits and a plurality of vertical signal lines.

FIG. 13 is a diagram illustrating an example of a cross-sectional configuration of the imaging unit illustrated in FIG. 6 in the horizontal direction.

FIG. 14 is a diagram illustrating an example of the cross-sectional configuration of the imaging unit illustrated in FIG. 6 in the horizontal direction.

FIG. 15 is a diagram illustrating an example of a wiring line layout of the imaging unit illustrated in FIG. 6 within a horizontal plane.

FIG. 16 is a diagram illustrating an example of the wiring line layout of the imaging unit illustrated in FIG. 6 within the horizontal plane.

FIG. 17 is a diagram illustrating an example of the wiring line layout of the imaging unit illustrated in FIG. 6 within the horizontal plane.

FIG. 18 is a diagram illustrating an example of the wiring line layout of the imaging unit illustrated in FIG. 6 within the horizontal plane.

FIG. 19A is a diagram illustrating an example of a process of manufacturing the imaging unit illustrated in FIG. 6.

FIG. 19B is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19A.

FIG. 19C is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19B.

FIG. 19D is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19C.

FIG. 19E is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19D.

FIG. 19F is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19E.

FIG. 19G is a diagram illustrating an example of a manufacturing process subsequent to FIG. 19F.

FIG. 20A is a diagram illustrating an example of a process of manufacturing a semiconductor device that is a reference example.

FIG. 20B is a diagram illustrating an example of a manufacturing process subsequent to FIG. 20A.

FIG. 21A is a diagram describing a main portion of a process of manufacturing of the semiconductor device according to the present embodiment.

FIG. 21B is a diagram illustrating an example of a manufacturing modification subsequent to FIG. 21A.

FIG. 22 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 1 of the present disclosure in the vertical direction.

FIG. 23 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 2 of the present disclosure in the vertical direction.

FIG. 24 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 3 of the present disclosure in the horizontal direction.

FIG. 25 is a diagram illustrating another example of the cross-sectional configuration of the imaging unit according to the modification example 3 of the present disclosure in the horizontal direction.

FIG. 26 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 4 of the present disclosure in the horizontal direction.

FIG. 27 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 5 of the present disclosure in the horizontal direction.

FIG. 28 is a diagram illustrating an example of a cross-sectional configuration of an imaging unit according to a modification example 6 of the present disclosure in the horizontal direction.

FIG. 29 is a diagram illustrating another example of the cross-sectional configuration of the imaging unit according to the modification example 6 of the present disclosure in the horizontal direction.

FIG. 30 is a diagram illustrating another example of the cross-sectional configuration of the imaging unit according to the modification example 6 of the present disclosure in the horizontal direction.

FIG. 31 is a diagram illustrating an example of a circuit configuration of an imaging unit according to a modification example 7 of the present disclosure.

FIG. 32 is a diagram illustrating an example in which an imaging unit according to a modification example 8 of the present disclosure in FIG. 31 includes three substrates that are stacked.

FIG. 33 is a diagram illustrating an example in which a logic circuit according to a modification example 9 of the present disclosure is separately formed in a substrate provided with a sensor pixel and a substrate provided with a readout circuit.

FIG. 34 is a diagram illustrating an example in which a logic circuit according to a modification example 10 of the present disclosure is formed on a third substrate.

FIG. 35 is a diagram illustrating an example of a schematic configuration of an imaging system including the imaging unit according to any of the embodiment described above and the modification examples thereof.

FIG. 36 is a diagram illustrating an example of an imaging procedure in the imaging system in FIG. 35.

FIG. 37 is a diagram illustrating an overview of configuration examples of a non-stacked solid-state imaging unit and a stacked solid-state imaging unit to which the technology according to the present disclosure may be applied.

FIG. 38 is a cross-sectional view illustrating a first configuration example of the stacked solid-state imaging unit.

FIG. 39 is a cross-sectional view illustrating a second configuration example of the stacked solid-state imaging unit.

FIG. 40 is a cross-sectional view illustrating a third configuration example of the stacked solid-state imaging unit.

FIG. 41 is a cross-sectional view illustrating another configuration example of the stacked solid-state imaging unit to which the technology according to the present disclosure may be applied.

FIG. 42 is a block diagram depicting an example of schematic configuration of a vehicle control system.

FIG. 43 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section.

FIG. 44 is a view depicting an example of a schematic configuration of an endoscopic surgery system.

FIG. 45 is a block diagram depicting an example of a functional configuration of a camera head and a camera control unit (CCU).

MODES FOR CARRYING OUT THE INVENTION

The following describes an embodiment of the present disclosure in detail with reference to the drawings. The following description is a specific example of the present disclosure, but the present disclosure is not limited to the following modes. In addition, the present disclosure is not also limited to the disposition, dimensions, dimension ratios, and the like of the respective components illustrated in the respective diagrams. It is to be noted that description is given in the following order.

1. Embodiment (An example of a semiconductor device having, above gaps provided between a plurality of wiring lines extending in one direction, a stack region in which insulating films including different materials are stacked)

1-1. Configuration of Semiconductor Device 1-2. Method of Manufacturing Semiconductor Device 1-3. Configuration of Imaging Unit 1-4. Method of Manufacturing Imaging Unit 1-5. Workings and Effects 2. Modification Examples

2-1. Modification Example 1 (An example in which planar TG is used) 2-2. Modification Example 2 (An example in which Cu—Cu junction is used at a panel outer edge) 2-3. Modification Example 3 (An example in which an offset is provided between a sensor pixel and a readout circuit) 2-4. Modification Example 4 (An example in which a silicon substrate provided with a readout circuit has an island shape) 2-5. Modification Example 5 (An example in which a silicon substrate provided with a readout circuit has an island shape) 2-6. Modification Example 6 (An example in which FD is shared by four sensor pixels) 2-7. Modification Example 7 (An example in which a column signal processing circuit includes a typical column ADC circuit) 2-8. Modification Example 8 (An example in which an imaging unit includes three substrates that are stacked) 2-9. Modification Example 9 (An example in which a logic circuit is provided on a first substrate and a second substrate) 2-10. Modification Example 10 (An example in which a logic circuit is provided on a third substrate)

3. Application Examples 4. Practical Application Examples 1. Embodiment

FIG. 1 illustrates an example of a cross-sectional configuration of a semiconductor device (a semiconductor device 100) according to an embodiment of the present disclosure in the vertical direction. FIG. 2 illustrates an example of a cross-sectional configuration of the whole of the semiconductor device 100 illustrated in FIG. 1 in the horizontal direction. The semiconductor device 100 has, for example, a multilayer wiring structure in which a plurality of wiring layers is stacked. The semiconductor device 100 is applicable, for example, to the imaging unit 1 described below. In the semiconductor device 100 according to the present embodiment, an insulating layer 132 is stacked on a wiring layer 123. The wiring layer 123 includes a plurality of wiring lines (e.g., a wiring line 123X1 to a wiring line 123X5 and a wiring line 123Y) extending in one direction (e.g., the Z axis direction). The insulating layer 132 forms gaps G, for example, between the wiring line 123X1 to the wiring line 123X5. The insulating layer 132 has a stack region 100Y partially within the plane. An insulating film 132A and an insulating film 132B are stacked in the stack region 100Y. The insulating film 132A and the insulating film 132B include materials different from each other. This stack region 100Y is provided above the gaps G provided between the wiring line 123X1 to the wiring line 123X5.

1-1. Configuration of Semiconductor Device

The semiconductor device 100 has a configuration in which a first layer 110, a second layer 120, and a third layer 130 are stacked in this order on a support substrate 101 including, for example, a silicon substrate. The first layer 110 and the second layer 120 respectively include a wiring layer 113 and the wiring layer 123. The wiring layer 113 and the wiring layer 123 each include a plurality of wiring lines.

In the first layer 110, an insulating layer 111 and an insulating layer 112 are stacked in this order. The wiring layer 113 is formed to be embedded in the insulating layer 112. The wiring layer 113 includes a plurality of wiring lines (e.g., a wiring line 113X1 to a wiring line 113X5 and a wiring line 113Y). The insulating layer 111 is formed by using, for example, silicon oxide (SiO_(x)), silicon nitride (SiN_(x)), or the like. The insulating layer 112 is formed by using, for example, a low dielectric constant material (Low-k material) having a relative dielectric constant (k) of 2.9 or less. Specific examples of a material of the insulating layer 112 include SiOC or the like. The wiring layer 113 includes, for example, a plurality of wiring lines extending in one direction. The wiring layer 113 includes, for example, the wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y extending in the Z axis direction. The wiring line 113X1 to the wiring line 113X5 are formed side by side, for example, with Line (L)/Space (S)=80/80 nm. The wiring line 113X1 to the wiring line 113X5 are included, for example, in a high wiring density region 100X of the first layer 110. The wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y are formed to be embedded, for example, in an opening 112H provided in the insulating layer 112. The wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y each include, for example, a barrier metal 113A formed on the side surface and the bottom surface of the opening 112H and a metal film 113B with which the opening 112H is filled. Examples of a material of the barrier metal 113A include Ti (titanium) or Ta (tantalum) alone, an alloy thereof, or the like. Examples of a material of the metal film 113B include a metal material mainly including a low resistance metal such as Cu (copper), W (tungsten), or aluminum (Al).

In the second layer 120, an insulating layer 121 and an insulating layer 122 are stacked in this order. The wiring layer 123 is formed to be embedded in the insulating layer 122. The wiring layer 123 includes a plurality of wiring lines (e.g., a wiring line 123X1 to a wiring line 123X5 and a wiring line 123Y). This wiring layer 123 corresponds to a specific example of a “first wiring layer” according to the present disclosure. The insulating layer 121 is formed by using, for example, SiCN. The insulating layer 122 is formed by using, for example, a Low-k material having a relative dielectric constant (k) of 2.9 or less. Specific examples of a material of the insulating layer 122 include SiOC or the like. The wiring layer 123 includes, for example, a plurality of wiring lines extending in one direction. The wiring layer 123 includes, for example, the wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y extending in the Z axis direction as with the wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y. The wiring line 123X1 to the wiring line 123X5 are formed side by side, for example, with Line (L)/Space (S)=80/80 nm. The wiring line 123X1 to the wiring line 123X5 are included, for example, in the high wiring density region 100X of the second layer 120. The wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y are formed to be embedded, for example, in an opening 122H1 provided in the insulating layer 122. The wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y each include, for example, a barrier metal 123A formed on the side surface and the bottom surface of the opening 122H1 and a metal film 123B with which the opening 122H1 is filled. Examples of a material of the barrier metal 123A include Ti (titanium) or Ta (tantalum) alone, an alloy thereof, or the like. Examples of a material of the metal film 123B include a metal material mainly including a low resistance metal such as Cu (copper), W (tungsten), or aluminum (Al). The wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y and the wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y of the wiring layer 113 are stacked in the Y axis direction. The wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y and the wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y of the wiring layer 113 are electrically coupled to each other at predetermined positions, for example, through a via V1.

An insulating layer 131 and the insulating layer 132 are stacked in this order in the third layer 130. The insulating layer 131 is formed by using, for example, SiCN. In the present embodiment, the insulating layer 122 included in the second layer 120 has an opening 122H2 between wiring lines (e.g., between the wiring line 123X2 and the wiring line 123X3, between the wiring line 123X3 and the wiring line 123X4, or between the wiring line 123X4 and the wiring line 123X5) in the high wiring density region 100X. The insulating layer 131 is continuously provided, for example, on the upper surfaces of the insulating layer 122, the wiring line 123X1 to the wiring line 123X5, and the wiring line 123Y and the side surface and the bottom surface of the opening 122H2. The insulating layer 132 is provided on the insulating layer 131. The opening 122H2 provided between wiring lines in the high wiring density region 100X of the second layer 120 is closed by the insulating layer 132. This forms the gaps G between wiring lines (e.g., between the wiring line 123X2 and the wiring line 123X3, between the wiring line 123X3 and the wiring line 123X4, and between the wiring line 123X4 and the wiring line 123X5) of the second layer 120.

It is to be noted that the openings 122H2 are formed to avoid the vias V1 that electrically couple the wiring line 113X1 to the wiring line 113X5 and the wiring line 123X1 to the wiring line 123X5. In other words, a region (a gap formation region 100Z) in which the gap G is formed is provided in a region in which the via V1 is not formed in the high wiring density region 100X in which the wiring line 123X1 to the wiring line 123X5 are formed side by side as illustrated in FIG. 2.

The insulating film 132A and the insulating film 132B are stacked in the insulating layer 132 partially within the plane. The insulating film 132A and the insulating film 132B include different materials. This insulating layer 132 corresponds to a specific example of a “first insulating layer” according to the present disclosure and the insulating film 132A and the insulating film 132B respectively correspond to specific examples of the “first insulating film” and a “second insulating film” according to the present disclosure. The insulating film 132A is formed by using, for example, a Low-k material having a relative dielectric constant (k) of 2.9 or less. Specific examples of a material of the insulating film 132A include SiOC or the like. It is preferable to use a material having a higher polishing rate, for example, than that of the insulating film 132A as a material of the insulating film 132B. Examples of such a material include silicon oxide (SiO_(x)), SiOC, SiOF, or SiON. It is to be noted that the insulating film 132B may be a single layer film including any one of the materials described above or may be formed as a stacked film including two or more of the materials described above. Although described in detail below, this fills a step difference of the insulating film 132A with the insulating film 132B. The step difference of the insulating film 132A is formed above the opening 122H2 by a portion of the insulating film 132A entering the opening 122H2 along the side surface to close the opening 122H2. In other words, the step difference of the insulating film 132A is formed above the gap formation region 100Z. The opening 122H2 is provided between wiring lines of the second layer 120. This makes it possible to obtain the insulating layer 132 having a flat surface.

It is to be noted that a wiring layer including a plurality of wiring lines may be formed to be embedded in the surface of the insulating layer 132 in the third layer 130 as with the first layer 110 and the second layer 120. FIG. 3 illustrates another example of the semiconductor device 100 according to the present disclosure. A wiring layer 133 is formed to be embedded in the insulating layer 132 included in the third layer 130 of the semiconductor device 100 illustrated in FIG. 3. A fourth layer 140 including a wiring layer 143 is further stacked on the third layer 130. The wiring layer 133 includes a plurality of wiring lines (e.g., a wiring line 133X1 to a wiring line 133X5 and a wiring line 133Y).

The wiring layer 133 includes, for example, a plurality of wiring lines extending in one direction. The wiring layer 133 includes, for example, the wiring line 133X1 to the wiring line 133X5 and the wiring line 133Y extending in the Z axis direction as with the wiring line 113X1 to the wiring line 113X5, the wiring line 113Y, and the like. This wiring layer 133 corresponds to a specific example of a “second wiring layer” according to the present disclosure. The wiring line 133X1 to the wiring line 133X5 are formed side by side, for example, with Line (L)/Space (S)=80/80 nm. The wiring line 133X1 to the wiring line 133X5 are included, for example, in the high wiring density region 100X of the third layer 130. At least a portion of each of the wiring line 133X1 to the wiring line 133X5 is formed, for example, in the stack region 100Y in which the insulating film 132A and the insulating film 132B described above are stacked. The wiring line 133X1 to the wiring line 133X5 and the wiring line 133Y are formed to be embedded, for example, in an opening 132H provided in the insulating layer 132. The wiring line 133X1 to the wiring line 133X5 and the wiring line 133Y each include, for example, a barrier metal 133A formed on the side surface and the bottom surface of the opening 132H and a metal film 133B with which the opening 122H1 is filled. Examples of a material of the barrier metal 133A include Ti (titanium) or Ta (tantalum) alone, an alloy thereof, or the like. Examples of a material of the metal film 133B include a metal material mainly including a low resistance metal such as Cu (copper), W (tungsten), or aluminum (Al). The wiring line 133Y and the wiring line 123Y of the wiring layer 123 are electrically coupled, for example, through a via V2.

In the fourth layer 140, an insulating layer 141 and an insulating layer 142 are stacked in this order. The wiring layer 143 is formed to be embedded in the insulating layer 142. The wiring layer 143 includes a plurality of wiring lines (e.g., a wiring line 143X1 to a wiring line 143X5 and a wiring line 143Y). The insulating layer 141 is formed by using, for example, SiCN. The insulating layer 142 is formed by using, for example, a Low-k material having a relative dielectric constant (k) of 2.9 or less. Specific examples of a material of the insulating layer 142 include SiOC or the like. The wiring layer 143 includes, for example, a plurality of wiring lines extending in one direction. The wiring layer 143 includes, for example, the wiring line 143X1 to the wiring line 143X5 and the wiring line 143Y extending in the Z axis direction as with the wiring line 113X1 to the wiring line 113X5, the wiring line 113Y, and the like. The wiring line 143X1 to the wiring line 143X5 are formed side by side, for example, with Line (L)/Space (S)=80/80 nm. The wiring line 143X1 to the wiring line 143X5 are included, for example, in the high wiring density region 100X of the fourth layer 140. The wiring line 143X1 to the wiring line 143X5 and the wiring line 143Y are formed to be embedded, for example, in an opening 142H provided in the insulating layer 142. The wiring line 143X1 to the wiring line 143X5 and the wiring line 143Y each include, for example, a barrier metal 143A formed on the side surface and the bottom surface of the opening 142H and a metal film 143B with which the opening 142H is filled. Examples of a material of the barrier metal 143A include Ti (titanium) or Ta (tantalum) alone, an alloy thereof, or the like. Examples of a material of the metal film 143B include a metal material mainly including a low resistance metal such as Cu (copper), W (tungsten), or aluminum (Al). The wiring line 143Y and the wiring line 133Y of the wiring layer 133 are electrically coupled, for example, through a via V3.

1-2. Method of Manufacturing Semiconductor Device

First, the insulating layer 111 and the insulating layer 112 are formed in order on the support substrate 101. After that, the wiring layer 113 is formed to be embedded in the insulating layer 112 and the first layer 110 is formed. The wiring layer 113 includes the wiring line 113X1 to the wiring line 113X5 and the wiring line 113Y. Subsequently, the insulating layer 121 and the insulating layer 122 are formed in order on the first layer 110. Next, as illustrated in FIG. 4A, the insulating layer 122 is patterned, for example, by photolithography and etching and the opening 122H1 is formed.

Subsequently, as illustrated in FIG. 4B, a film of the barrier metal 123A is formed on the side surface and the bottom surface of the opening 122H1 by using, for example, sputtering. After that, the metal film 123B is formed in the opening 122H1 by using, for example, plating and the surface is then grinded. This forms the second layer 120 on the surface of the insulating layer 122. The wiring line 123X1 to the wiring line 123X5 and the wiring line 123Y are provided to be embedded in the second layer 120.

Next, as illustrated in FIG. 4C, a SiCN film 131A is formed on the second layer 120 by using, for example, CVD. After that, the SiCN film 131A and the insulating layer 122 are patterned, for example, by photolithography and etching. The respective openings 122H2 are formed between the wiring line 123X2 and the wiring line 123X3, between the wiring line 123X3 and the wiring line 123X4, and between the wiring line 123X4 and the wiring line 123X5.

Subsequently, as illustrated in FIG. 4D, a SiCN film is formed again on the second layer 120 and the side surface and the bottom surface of each of the openings 122H2 by using, for example, CVD. The insulating layer 131 is formed that has, for example, a film thickness of 30 nm to 50 nm. After that, as illustrated in FIG. 4E, the insulating film 132A is formed on the whole surface of the second layer 120 by using, for example, CVD. The insulating film 132A includes, for example, SiOC. The insulating film 132A has, for example, a film thickness of 400 nm to 500 nm. This closes the opening 122H2 and forms the gaps G between the wiring line 123X2 and the wiring line 123X3, between the wiring line 123X3 and the wiring line 123X4, and between the wiring line 123X4 and the wiring line 123X5.

Next, as illustrated in FIG. 4F, the insulating film 132B is formed on the insulating film 132A by using, for example, CVD. The insulating film 132B includes, for example, SiO_(x). The insulating film 132B has, for example, a film thickness of 200 nm to 300 nm. After that, as illustrated in FIG. 4G, the insulating film 132B is polished by using, for example, a CMP (Chemical Mechanical Polishing) method. This planarizes the surface of the insulating layer 132. The stack region 100Y is formed above the gaps G (above the gap formation region 100Z). The respective gaps G are formed, for example, between the wiring line 123X2 and the wiring line 123X3, between the wiring line 123X3 and the wiring line 123X4, and between the wiring line 123X4 and the wiring line 123X5. The insulating film 132A and the insulating film 132B are stacked in the stack region 100Y. This completes the semiconductor device 100 illustrated in FIG. 1.

Further, in a case where the third layer 130 and the fourth layer 140 respectively including the wiring layer 133 and the wiring layer 143 are formed in order on the second layer 120 as in the semiconductor device 100 illustrated in FIG. 3, the semiconductor device 100 is manufactured, for example, as follows.

First, as illustrated in FIG. 5A, the insulating layer 132 is patterned, for example, by photolithography and etching and the opening 132H is formed. Subsequently, as illustrated in FIG. 5B, a film of the barrier metal 133A is formed on the side surface and the bottom surface of the opening 132H by using, for example, sputtering. After that, the metal film 133B is formed in the opening 132H by using, for example, plating and the surface is then grinded. This forms the wiring layer 133 on the surface of the insulating layer 132. The wiring layer 133 includes the wiring line 133X1 to the wiring line 133X5 and the wiring line 133Y.

Next, as illustrated in FIG. 5C, 141 including a SiCN film and having, for example, a film thickness of 30 nm to 50 nm is formed on the third layer 130 by using, for example, CVD. After that, the insulating layer 142 is formed that includes, for example, SiOC (an example of a material) and has, for example, a film thickness of 400 nm to 500 nm. Subsequently, the insulating layer 142 is patterned, for example, by photolithography and etching and the opening 142H is formed. After that, the wiring layer 143 is formed by using, for example, a method similar to that of the wiring layer 133. This completes the semiconductor device 100 illustrated in FIG. 3.

1-3. Configuration of Imaging Unit

FIG. 6 illustrates an example of a cross-sectional configuration of an imaging unit (an imaging unit 1) according to an embodiment of the present disclosure in the vertical direction. FIG. 7 illustrates an example of a schematic configuration of the imaging unit 1 illustrated in FIG. 6. The imaging unit 1 is an imaging unit having a three-dimensional structure in which a first substrate 10 and a second substrate 20 are stacked. The first substrate 10 includes a sensor pixel 12 in a semiconductor substrate 11. The second substrate 20 includes a readout circuit 22 in a semiconductor substrate 21. The sensor pixel 12 performs photoelectric conversion. The readout circuit 22 outputs an image signal based on electric charge outputted from the sensor pixel 12. The multilayer wiring structure described for the semiconductor device 100 described above is applied, for example, to a wiring layer 56 stacked on the semiconductor substrate 21.

In the imaging unit 1, three substrates (the first substrate 10, the second substrate 20, and a third substrate 30) are stacked in this order.

As described above, the first substrate 10 includes the plurality of sensor pixels 12 on the semiconductor substrate 11. Each of the plurality of sensor pixels 12 performs photoelectric conversion. The semiconductor substrate 11 corresponds to a specific example of a “first semiconductor substrate” according to the present disclosure. The plurality of sensor pixels 12 is provided in matrix in a pixel region 13 on the first substrate 10. The second substrate 20 includes the one readout circuit 22 for every four sensor pixels 12 on the semiconductor substrate 21. The readout circuit 22 outputs a pixel signal based on electric charge outputted from each of the sensor pixels 12. The semiconductor substrate 21 corresponds to a specific example of a “second semiconductor substrate” according to the present disclosure. The second substrate 20 includes a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 includes a logic circuit 32 on a semiconductor substrate 31. The logic circuit 32 processes a pixel signal. The semiconductor substrate 31 corresponds to a specific example of a “third semiconductor substrate” according to the present disclosure. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each of the sensor pixels 12 to the outside. In the logic circuit 32, for example, a low resistance region that includes a silicide and is formed by using Salicide (Self Aligned Silicide) process such as CoSi₂ and NiSi may be formed on the surface of an impurity diffusion region in contact with a source electrode and a drain electrode.

The vertical drive circuit 33 selects, for example, the plurality of sensor pixels 12 row by row in order. The column signal processing circuit 34 performs, for example, a correlated double sampling (Correlated Double Sampling: CDS) process on a pixel signal outputted from each of the sensor pixels 12 in a row selected by the vertical drive circuit 33. The column signal processing circuit 34 performs, for example, the CDS process, thereby extracting the signal level of the pixel signal. The column signal processing circuit 34 holds pixel data corresponding to the amount of light received by each of the sensor pixels 12. The horizontal drive circuit 35 outputs, for example, the pieces of pixel data held in the column signal processing circuit 34 to the outside in order. The system control circuit 36 controls, for example, the driving of each of the blocks (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

FIG. 8 illustrates examples of the sensor pixel 12 and the readout circuit 22. The following describes a case where the four sensor pixels 12 share the one readout circuit 22 as illustrated in FIG. 8. Here, the “share” means that outputs of the four sensor pixels 12 are inputted to the common readout circuit 22.

Each of the sensor pixels 12 includes mutually common components. In FIG. 8, to distinguish components of the respective sensor pixels 12 from each other, an identification number (1, 2, 3, or 4) is assigned to the end of the symbol of a component of each of the sensor pixels 12. In a case where the components of the respective sensor pixels 12 have to be distinguished from each other, the following assigns an identification number to the end of the symbol of a component of each of the sensor pixels 12. However, in a case where there is no need to distinguish the components of the respective sensor pixels 12 from each other, an identification number at the end of the symbol of a component of each of the sensor pixels 12 is omitted.

Each of the sensor pixels 12 includes, for example, photodiode PD, a transfer transistor TR electrically coupled to the photodiode PD, and a floating diffusion FD that temporarily holds electric charge outputted from the photodiode PD through the transfer transistor TR. The photodiode PD corresponds to a specific example of a “photoelectric conversion element” according to the present disclosure. The photodiode PD performs photoelectric conversion to generate electric charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically coupled to the source of the transfer transistor TR and the anode of the photodiode PD is electrically coupled to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically coupled to the floating diffusion FD and the gate of the transfer transistor TR is electrically coupled to the pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

The floating diffusions FD of the respective sensor pixels 12 that share the one readout circuit 22 are electrically coupled to each other and are electrically coupled to the input end of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. It is to be noted that the selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input end of the readout circuit 22) is electrically coupled to the floating diffusion FD and the drain of the reset transistor RST is electrically coupled to a power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically coupled to the pixel drive line 23. The source of the amplification transistor AMP is electrically coupled to the drain of the selection transistor SEL and the gate of the amplification transistor AMP is electrically coupled to the source of the reset transistor RST. The source of the selection transistor SEL (the output end of the readout circuit 22) is electrically coupled to the vertical signal line 24 and the gate of the selection transistor SEL is electrically coupled to the pixel drive line 23.

In a case where the transfer transistor TR is turned on, the transfer transistor TR transfers the electric charge of the photodiode PD to the floating diffusion FD. The gate (a transfer gate TG) of the transfer transistor TR extends to penetrate a p well 42 from the surface of the semiconductor substrate 11 to such a depth as to reach PD 41, for example, as illustrated in FIG. 6. The reset transistor RST resets the electric potential of the floating diffusion FD to a predetermined electric potential. In a case where the reset transistor RST is turned on, the electric potential of the floating diffusion FD is reset to the electric potential of the power supply line VDD. The selection transistor SEL controls the timing of outputting a pixel signal from the readout circuit 22. The amplification transistor AMP generates, as a pixel signal, a signal of a voltage corresponding to the level of electric charge held in the floating diffusion FD. The amplification transistor AMP is included in a source-follower type amplifier and outputs a pixel signal of a voltage corresponding to the level of electric charge generated in the photodiode PD. In a case where the selection transistor SEL is turned on, the amplification transistor AMP amplifies the electric potential of the floating diffusion FD and outputs a voltage corresponding to the electric potential to the column signal processing circuit 34 through the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

It is to be noted that, as illustrated in FIG. 9, the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically coupled to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically coupled to the drain of the amplification transistor AMP and the gate of the selection transistor SEL is electrically coupled to the pixel drive line 23. The source of the amplification transistor AMP (the output end of the readout circuit 22) is electrically coupled to the vertical signal line 24 and the gate of the amplification transistor AMP is electrically coupled to the source of the reset transistor RST. In addition, as illustrated in FIGS. 10 and 11, an FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

The FD transfer transistor FDG is used to switch the conversion efficiency. In general, a pixel signal is small in shooting in a dark place. In a case where electric charge-voltage conversion is performed on the basis of Q=CV, the floating diffusion FD having larger capacitance (FD capacitance C) results in smaller V that is obtained in a case of conversion to a voltage by the amplification transistor AMP. Meanwhile, a bright place offers a large pixel signal. It is therefore not possible for the floating diffusion FD to receive the electric charge of the photodiode PD unless the FD capacitance C is large. Further, the FD capacitance C has to be large to prevent V from being too large (i.e., to make V small) in a case of conversion to a voltage by the amplification transistor AMP. Taking these into consideration, in a case where the FD transfer transistor FDG is turned on, the gate capacitance for the FD transfer transistor FDG is increased. This causes the whole FD capacitance C to be large. Meanwhile, in a case where the FD transfer transistor FDG is turned off, the whole FD capacitance C becomes small. In this way, switching the FD transfer transistor FDG on and off enables the FD capacitance C to be variable. This makes it possible to switch the conversion efficiency.

FIG. 12 illustrates an example of a coupling mode between the plurality of readout circuits 22 and the plurality of vertical signal lines 24. In a case where the plurality of readout circuits 22 is disposed side by side in the direction in which the vertical signal lines 24 extend (e.g., the column direction), the plurality of vertical signal lines 24 may be assigned one by one for the respective readout circuits 22. In a case where the four readout circuits 22 are disposed side by side in the direction in which the vertical signal lines 24 extend (e.g., the column direction), for example, as illustrated in FIG. 12, the four vertical signal lines 24 may be assigned one by one for the respective readout circuits 22. It is to be noted that an identification number (1, 2, 3, or 4) is assigned to the end of the symbol of each of the vertical signal lines 24 to distinguish the respective vertical signal lines 24 in FIG. 12.

Next, a cross-sectional configuration of the imaging unit 1 in the vertical direction is described with reference to FIG. 6. As described above, the imaging unit 1 has a configuration in which the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order and further includes a color filter 40 and a light receiving lens 50 on the back surface (light incidence surface) side of the first substrate 10. The color filter 40 and the light receiving lens 50 are each provided one by one, for example, for each of the sensor pixels 12. In other words, the imaging unit 1 is a back-illuminated imaging unit.

The first substrate 10 includes an insulating layer 46 that is stacked on the front surface (a surface 11S1) of the semiconductor substrate 11. The first substrate 10 includes the insulating layer 46 as a portion of an interlayer insulating film 51. The insulating layer 46 is provided between the semiconductor substrate 11 and the semiconductor substrate 21 described below. The semiconductor substrate 11 includes a silicon substrate. The semiconductor substrate 11 includes, for example, the p well 42 in a portion of the front surface and near the front surface and includes the PD 41 of an electric conductivity type different from that of the p well 42 in another region (a region deeper than the p well 42). The p well 42 includes a p-type semiconductor region. The PD 41 includes a semiconductor region of an electric conductivity type (specifically, n-type) different from that of the p well 42. The semiconductor substrate 11 includes, in the p well 42, the floating diffusion FD as a semiconductor region of an electric conductivity type (specifically, n-type) different from that of the p well 42.

The first substrate 10 includes the photodiode PD, the transfer transistor TR, and the floating diffusion FD for each of the sensor pixels 12. The first substrate 10 has a configuration in which the transfer transistor TR and the floating diffusion FD are provided on a portion of the semiconductor substrate 11 on the surface 11S1 side (the opposite side to the light incidence surface or the second substrate 20 side). The first substrate 10 includes an element separation section 43 that separates the sensor pixels 12 from each other. The element separation section 43 is formed to extend in the normal direction of the semiconductor substrate 11 (the direction vertical to the front surface of the semiconductor substrate 11). The element separation section 43 is provided between the two sensor pixels 12 adjacent to each other. The element separation section 43 electrically separates the adjacent sensor pixels 12 from each other. The element separation section 43 includes, for example, silicon oxide. The element separation section 43 penetrates, for example, the semiconductor substrate 11. The first substrate 10 further includes, for example, a p well layer 44 that is the side surface of the element separation section 43 and is in contact with the surface on the photodiode PD side. The p well layer 44 includes a semiconductor region of an electric conductivity type (specifically, p-type) different from that of the photodiode PD. The first substrate 10 further includes, for example, a fixed electric charge film 45 that is in contact with the back surface (a surface 11S2 or the other surface) of the semiconductor substrate 11. The fixed electric charge film 45 has negative fixed electric charge to suppress the generation of a dark current due to the interface state of the semiconductor substrate 11 on the light receiving surface side. The fixed electric charge film 45 is formed by using, for example, an insulating film having negative fixed electric charge. Examples of a material of such an insulating film include hafnium oxide, zircon oxide, aluminum oxide, titanium oxide, and tantalum oxide. An electric field induced by the fixed electric charge film 45 forms a hole accumulation layer at the interface of the semiconductor substrate 11 on the light receiving surface side. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed electric charge film 45 and is provided at a position opposed to the sensor pixel 12 with the fixed electric charge film 45 interposed in between. The light receiving lens 50 is provided, for example, in contact with the color filter 40 and is provided at a position opposed to the sensor pixel 12 with the color filter 40 and the fixed electric charge film 45 interposed in between.

The second substrate 20 includes an insulating layer 52 that is stacked on the semiconductor substrate 21. The insulating layer 52 and the second substrate 20 each include the insulating layer 52 as a portion of the interlayer insulating film 51. The insulating layer 52 is provided between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 includes a silicon substrate. The second substrate 20 includes the one readout circuit 22 for every four sensor pixels 12. The second substrate 20 has a configuration in which the readout circuit 22 is provided on a portion of the semiconductor substrate 21 on the front surface (a surface 21S1 opposed to the third substrate 30 or one surface) side. The second substrate 20 is bonded to the first substrate 10 with the back surface (a surface 2152) of the semiconductor substrate 21 opposed to the front surface (the surface 1151) of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 in a face-to-back manner. The second substrate 20 further includes an insulating layer 53 in the same layer as the semiconductor substrate 21. The insulating layer 53 penetrates the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as a portion of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side surface of a through wiring line 54 described below.

A stacked body including the first substrate 10 and the second substrate 20 includes the interlayer insulating film 51 and the through wiring line 54 provided in the interlayer insulating film 51. The through wiring line 54 corresponds to a specific example of a “first through wiring line” according to the present disclosure. The stacked body described above includes the one through wiring line 54 for each of the sensor pixels 12. The through wiring line 54 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically coupled to each other by the through wiring line 54. Specifically, the through wiring line 54 is electrically coupled to the floating diffusion FD and a coupling wiring line 55 described below.

The stacked body including the first substrate 10 and the second substrate 20 further includes through wiring lines 47 and 48 (see FIG. 13 described below) provided in the interlayer insulating film 51. Each of the through wiring lines 47 and 48 corresponds to a specific example of a “second through wiring line” according to the present disclosure. The stacked body described above includes the one through wiring line 47 and the one through wiring line 48 for each of the sensor pixels 12. Each of the through wiring lines 47 and 48 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically coupled to each other by the through wiring lines 47 and 48. Specifically, the through wiring line 47 is electrically coupled to the p well 42 of the semiconductor substrate 11 and to a wiring line in the second substrate 20. The through wiring line 48 is electrically coupled to the transfer gate TG and the pixel drive line 23.

The second substrate 20 includes, for example, a plurality of coupling sections 59 in the insulating layer 52. The plurality of coupling sections 59 is electrically coupled to the readout circuit 22 and the semiconductor substrate 21. The second substrate 20 further includes, for example, the wiring layer 56 on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57 and the plurality of pixel drive lines 23 and the plurality of vertical signal lines 24. The plurality of pixel drive lines 23 and the plurality of vertical signal lines 24 are provided in the insulating layer 57. For example, the plurality of these pixel drive lines 23 corresponds to the wiring line 113X1 to the wiring line 113X5 in the semiconductor device 100 described above. The plurality of vertical signal lines 24 corresponds to the wiring line 123X1 to the wiring line 123X5 in the semiconductor device 100 described above. Although not illustrated in FIG. 6, the gaps G as illustrated in FIG. 1 are formed between the wiring lines of the plurality of vertical signal lines 24 in the insulating layer 57. Further, the insulating layer 57 has a stack region on a portion of the surface serving as a surface bonded, for example, to a wiring layer 62 described below. Insulating films (the insulating films 132A and 132B in FIG. 1) including different materials are stacked in the stack region. This stack region is provided between a plurality of pad electrodes 58, for example, in FIG. 6. The plurality of pad electrodes 58 is described below. The plurality of these pad electrodes 58 corresponds, for example, to the wiring line 133X1 to the wiring line 133X5 in the semiconductor device 100 described above. The wiring layer 56 further includes, for example, the plurality of coupling wiring lines 55 in the insulating layer 57. The one coupling wiring line 55 is provided for every four sensor pixels 12. The coupling wiring line 55 electrically couples the respective through wiring lines 54 to each other. The through wiring lines 54 are electrically coupled to the floating diffusions FD included in the four sensor pixels 12 that share the readout circuit 22. Here, the total number of through wiring lines 54 and 48 is larger than the total number of sensor pixels 12 included in the first substrate 10 and is twice as large as the total number of sensor pixels 12 included in the first substrate 10. In addition, the total number of through wiring lines 54, 48, and 47 is larger than the total number of sensor pixels 12 included in the first substrate 10 and is three times as large as the total number of sensor pixels 12 included in the first substrate 10.

The wiring layer 56 further includes, for example, the plurality of pad electrodes 58 in the insulating layer 57. Each of the pad electrodes 58 is formed by using, for example, a metal such as Cu (copper) and Al (aluminum). Each of the pad electrodes 58 is exposed from the surface of the wiring layer 56. Each of the pad electrodes 58 is used to electrically couple the second substrate 20 and the third substrate 30 and bond the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 is provided one by one, for example, for the respective pixel drive lines 23 and the respective vertical signal lines 24. Here, the total number of pad electrodes 58 (or the total number of junctions between the pad electrode 58 and a pad electrode 64 (described below) is smaller than the total number of sensor pixels 12 included in the first substrate 10.

The third substrate 30 includes, for example, an interlayer insulating film 61 that is stacked on the semiconductor substrate 31. It is to be noted that, as described below, the third substrate 30 is bonded to the second substrate 20 on the front surfaces. Therefore, in a case where the components in the third substrate 30 are described, the vertical relationship to be described is opposite to the vertical direction in the diagram. The semiconductor substrate 31 includes a silicon substrate. The third substrate 30 has a configuration in which the logic circuit 32 is provided on a portion of the semiconductor substrate 31 on the front surface (a surface 31S1) side. The third substrate 30 further includes, for example, the wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and the plurality of pad electrodes 64 that is provided in the insulating layer 63. The plurality of pad electrodes 64 is electrically coupled to the logic circuit 32. Each of the pad electrodes 64 is formed by using, for example, Cu (copper). Each of the pad electrodes 64 is exposed from the surface of the wiring layer 62. Each of the pad electrodes 64 is used to electrically couple the second substrate 20 and the third substrate 30 and bond the second substrate 20 and the third substrate 30 together. In addition, the pad electrode 64 does not necessarily have to be a plurality of pad electrodes. Even one pad electrode is able to be electrically coupled to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically coupled to each other by bonding the pad electrodes 58 and 64 to each other. In other words, the gate (the transfer gate TG) of the transfer transistor TR is electrically coupled to the logic circuit 32 through the through wiring line 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with the front surface (the surface 3151) of the semiconductor substrate 31 opposed to the front surface (the surface 2151) side of the semiconductor substrate 21. In other words, the third substrate 30 is bonded to the second substrate 20 in a face-to-face manner.

Each of FIGS. 13 and 14 illustrates an example of a cross-sectional configuration of the imaging unit 1 in the horizontal direction. The diagram on the upper side of each of FIGS. 13 and 14 is a diagram illustrating an example of a cross-sectional configuration taken along a cross section Sec1 in FIG. 1 and the diagram on the lower side of each of FIGS. 13 and 14 is a diagram illustrating an example of a cross-sectional configuration taken along a cross section Sec2 in FIG. 1. FIG. 13 exemplifies a configuration in which two sets of 2×2 or four sensor pixels 12 are arranged in a second direction H and FIG. 14 exemplifies a configuration in which four sets of 2×2 or four sensor pixels 12 are arranged in a first direction V and the second direction H. It is to be noted that a diagram illustrating an example of the front surface configuration of the semiconductor substrate 11 is superimposed on a diagram illustrating the example of the cross-sectional configuration taken along the cross section Sec1 in FIG. 1 and the insulating layer 46 is omitted in the cross-sectional view on the upper side of each of FIGS. 13 and 14. In addition, a diagram illustrating an example of the front surface configuration of the semiconductor substrate 21 is superimposed on a diagram illustrating the example of the cross-sectional configuration taken along the cross section Sec2 in FIG. 1 in the cross-sectional view on the lower side of each of FIGS. 13 and 14.

As illustrated in FIGS. 13 and 14, the plurality of through wiring lines 54, the plurality of through wiring lines 48, and the plurality of through wiring lines 47 are disposed side by side in a strip shape in the first direction V (the up/down direction in FIG. 13 and the left/right direction in FIG. 14) within the plane of the first substrate 10. It is to be noted that each of FIGS. 13 and 14 exemplifies a case where the plurality of through wiring lines 54, the plurality of through wiring lines 48, and the plurality of through wiring lines 47 are disposed side by side in two rows in the first direction V. The first direction V is parallel with one (e.g., the column direction) of two arrangement directions (e.g., the row direction and the column direction) of the plurality of sensor pixels 12 disposed in a matrix. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are disposed close to each other, for example, with the element separation section 43 interposed in between. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG are disposed to surround the four floating diffusions FD and the four transfer gates TG form, for example, an annular shape.

The insulating layer 53 includes a plurality of blocks extending in the first direction V. The semiconductor substrate 21 extends in the first direction V and includes a plurality of island-shaped blocks 21A disposed side by side in the second direction H orthogonal to the first direction V with the insulating layer 53 interposed in between. Each of the blocks 21A is provided, for example, with a plurality of sets of reset transistors RST, amplification transistors AMP, and selection transistors SEL. The one readout circuit 22 shared by the four sensor pixels 12 includes, for example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL in a region opposed to the four sensor pixels 12. The one readout circuit 22 shared by the four sensor pixels 12 includes, for example, the amplification transistor AMP in the left adjacent block 21A of the insulating layer 53 and the reset transistor RST and the selection transistor SEL in the right adjacent block 21A of the insulating layer 53.

Each of FIGS. 15, 16, 17 and 18 illustrates an example of a wiring line layout of the imaging unit 1 within the horizontal plane. Each of FIGS. 15 to 18 exemplifies a case where the one readout circuit 22 shared by the four sensor pixels 12 is provided in a region opposed to the four sensor pixels 12. The wiring lines illustrated in FIGS. 15 to 18 are provided, for example, in layers different from each other in the wiring layer 56.

The four through wiring lines 54 adjacent to each other are electrically coupled to the coupling wiring line 55, for example, as illustrated in FIG. 15. The four through wiring lines 54 adjacent to each other are further electrically coupled to the gate of the amplification transistor AMP included in the left adjacent block 21A of the insulating layer 53 and the gate of the reset transistor RST included in the right adjacent block 21A of the insulating layer 53 through the coupling wiring line 55 and the coupling section 59, for example, as illustrated in FIG. 15.

The power supply line VDD is disposed at positions opposed to the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 16. The power supply line VDD is electrically coupled to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each of the readout circuits 22 disposed side by side in the second direction H through the coupling section 59, for example, as illustrated in FIG. 16. The two pixel drive lines 23 are disposed at positions opposed to the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 16. One (a second control line) of the pixel drive lines 23 is a wiring line RSTG electrically coupled to the gate of the reset transistor RST of each of the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 16. The other (a third control line) of the pixel drive lines 23 is a wiring line SELG electrically coupled to the gate of the selection transistor SEL of each of the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 16. In each of the readout circuits 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically coupled to each other through a wiring line 25, for example, as illustrated in FIG. 16.

The two power supply lines VSS are disposed at positions opposed to the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 17. Each of the power supply lines VSS is electrically coupled to the plurality of through wiring lines 47 at positions opposed to the respective sensor pixels 12 disposed side by side in the second direction H, for example, as illustrated in FIG. 17. The four pixel drive lines 23 are disposed at positions opposed to the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 17. Each of the four pixel drive lines 23 is a wiring line TRG electrically coupled to the through wiring line 48 of the one sensor pixel 12 of the four sensor pixels 12 corresponding to each of the readout circuits 22 disposed side by side in the second direction H, for example, as illustrated in FIG. 17. In other words, the four pixel drive lines 23 (first control lines) are each electrically coupled to the gate (transfer gate TG) of the transfer transistor TR of each of the sensor pixels 12 disposed side by side in the second direction H. In FIG. 17, to distinguish the wiring lines TRG from each other, an identifier (1, 2, 3, or 4) is assigned to the end of each of the wiring lines TRG.

The vertical signal lines 24 are disposed at positions opposed to the readout circuits 22 disposed side by side in the first direction V, for example, as illustrated in FIG. 18. The vertical signal line 24 (an output line) is electrically coupled to the output end (the source of the amplification transistor AMP) of each of the readout circuits 22 disposed side by side in the first direction V, for example, as illustrated in FIG. 18.

1-4. Method of Manufacturing Imaging Unit

Next, a method of manufacturing the imaging unit 1 is described. Each of FIGS. 19A to 19G illustrates an example of a process of manufacturing the imaging unit 1.

First, the p well 42, the element separation section 43, and the p well layer 44 are formed on the semiconductor substrate 11. Next, the photodiode PD, the transfer transistor TR, and the floating diffusion FD are formed on the semiconductor substrate 11 (FIG. 19A). This forms the sensor pixel 12 on the semiconductor substrate 11. In this case, it is preferable to prevent a material having low heat resistance such as CoSi₂ and NiSi by a Salicide process from being used as an electrode material to be used for the sensor pixel 12. Rather, it is preferable to use a material having high heat resistance as an electrode material to be used for the sensor pixel 12. Examples of the material having high heat resistance include polysilicon. After that, the insulating layer 46 is formed on the semiconductor substrate 11 (FIG. 19A). In this way, the first substrate 10 is formed.

Next, the semiconductor substrate 21 is bonded onto the first substrate 10 (an insulating layer 46B) (FIG. 19B). After that, the semiconductor substrate 21 is thinned as necessary. In this case, the thickness of the semiconductor substrate 21 is set at a film thickness necessary to form the readout circuit 22. The thickness of the semiconductor substrate 21 is typically about several hundreds of nm. However, an FD (Fully Depletion) type is also available depending on the concept of the readout circuit 22. In that case, the semiconductor substrate 21 may have a thickness within a range from several nm to several μm.

Subsequently, the insulating layer 53 is formed in the same layer as the semiconductor substrate 21 (FIG. 19C). The insulating layer 53 is formed, for example, at a position opposed to the floating diffusion FD. For example, a slit (an opening 21H) that penetrates the semiconductor substrate 21 is formed in the semiconductor substrate 21 to separate the semiconductor substrate 21 into the plurality of blocks 21A. After that, the insulating layer 53 is formed to fill the slit. After that, the readout circuit 22 including the amplification transistor AMP and the like is formed in each of the blocks 21A of the semiconductor substrate 21 (FIG. 19C). In this case, in a case where a metal material having high heat resistance is used as an electrode material of the sensor pixel 12, it is possible to form the gate insulating film of the readout circuit 22 by thermal oxidation.

Next, the insulating layer 52 is formed on the semiconductor substrate 21. In this way, the interlayer insulating film 51 including the insulating layers 46, 52, and 53 is formed. Subsequently, through holes 51A and 51B are formed in the interlayer insulating film 51 (FIG. 19D). Specifically, the through hole 51B that extends through the insulating layer 52 is formed in a portion of the insulating layer 52 that is opposed to the readout circuit 22. In addition, the through hole 51A that extends through the interlayer insulating film 51 is formed in a portion of the interlayer insulating film 51 that is opposed to the floating diffusion FD (i.e., a portion opposed to the insulating layer 53).

Subsequently, embedding electrically conductive materials in the through holes 51A and 51B causes the through wiring line 54 to be formed in the through hole 51A and causes the coupling section 59 to be formed in the through hole 51B (FIG. 19E). Further, the coupling wiring line 55 that electrically couples the through wiring line 54 and the coupling section 59 to each other is formed on the insulating layer 52 (FIG. 19E). After that, the wiring layer 56 is formed on the insulating layer 52 (FIG. 19F). In this way, the second substrate 20 is formed.

Next, the second substrate 20 is bonded to the third substrate 30 with the front surface of the semiconductor substrate 21 opposed to the front surface side of the semiconductor substrate 31 (FIG. 19G). The logic circuit 32 and the wiring layer 62 are formed on the third substrate 30. In this case, the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 are bonded to each other, thereby electrically coupling the second substrate 20 and the third substrate 30 to each other. In this way, the imaging unit 1 is manufactured.

1-5. Workings and Effects

As described above, in recent years, as finer semiconductor integrated circuit elements are made, the intervals between the elements and the intervals between wiring lines that connect the elements have been narrower in semiconductor devices. The capacitance (parasitic capacitance) between wiring lines tends to increase. Therefore, in a typical semiconductor device, wiring lines in the stack direction are electrically insulated by using a Low-k material and there is provided a gap between wiring lines disposed side by side to decrease the parasitic capacitance between the wiring lines.

In such a semiconductor device, a step difference is formed on the surface of an insulating layer 1132 above gaps, for example, as illustrated in FIG. 20A. The insulating layer 1132 formed by using a Low-k material typically has a low polishing rate. In a case where the insulating layer 1132 having a step difference on a portion of the surface, for example, as illustrated in FIG. 20A is polished by using, for example, a CMP method, the portion of the step difference is preferentially polished as illustrated in FIG. 20B. This may deteriorate the global step difference or increase variations in the film thickness of the insulating layer 1132 within the plane. In a case where the global step difference deteriorates or the insulating layer 1132 varies in film thickness within the plane, this causes variations in the wiring capacitance in the semiconductor device or causes variations in the device characteristics between two or more semiconductor devices.

In contrast, in the present embodiment, the insulating layer 132 is formed as a stacked film. The insulating film 132A and the insulating film 132B are stacked in the stacked film partially within the plane. The insulating film 132A and the insulating film 132B include materials different from each other. The insulating layer 132 is stacked on the second layer 120 including, for example, the plurality of wiring line 123X1 to wiring line 123X5 and the wiring line 123Y formed side by side in the Z axis direction. The insulating layer 132 forms the gaps G between the plurality of wiring line 123X1 to wiring line 123X5. The stack region 100Y in which these insulating film 132A and insulating film 132B are stacked is provided above the gaps G formed between the plurality of wiring line 123X1 to wiring line 123X5.

In the semiconductor device 100 according to the present embodiment, the insulating film 132A is stacked on the second layer 120 including, for example, the plurality of wiring line 123X1 to wiring line 123X5 and the wiring line 123Y. After that, the insulating film 132B formed by using a material having a higher polishing rate than that of the insulating film 132A is further stacked as illustrated in FIG. 21A. After that, the surface is polished by using, for example, a CMP method, for example, as illustrated in FIG. 21B. This fills a step difference with the insulating film 132B and makes it possible to planarize the surface of the third layer 130. The step difference is formed on the surface of the insulating film 132A by the insulating film 132A entering the openings 122H2 in a case where the insulating film 132A is formed on the second layer 120. The openings 122H2 are formed between the plurality of wiring line 123X1 to wiring line 123X5. In other words, variations in the film thickness of the insulating layer 132 within the plane is reduced.

As described above, it is possible in the semiconductor device 100 according to the present embodiment, for example, as with the semiconductor device 100 illustrated in FIG. 3 to reduce variations in the wiring capacitance in a case where the plurality of wiring line 133X1 to wiring line 133X5 and the wiring line 133Y are formed in the insulating layer 132, for example, as with the wiring layer 133 of the second layer 120. The plurality of wiring line 133X1 to wiring line 133X5 and the wiring line 133Y are formed side by side, for example, in the Z axis direction. This makes it possible to provide the imaging unit 1 having superior device characteristics.

The following describes modification examples 1 to 10. It is to be noted that the following description denotes the same components as those of the embodiment described above with the same symbols and the descriptions thereof are omitted as appropriate.

2. Modification Examples 2-1. Modification Example 1

FIG. 22 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 1) of the embodiment described above in the vertical direction. In the present modification example, the transfer transistor TR includes a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p well 42, but is formed on the front surface of the semiconductor substrate 11 alone. Even in a case where the planar transfer gate TG is used for the transfer transistor TR, the imaging unit 1 has effects similar to those of the embodiment described above.

2-2. Modification Example 2

FIG. 23 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 2) of the embodiment described above in the vertical direction. In the present modification example, the second substrate 20 and the third substrate 30 are electrically coupled in a region opposed to a peripheral region 14 on the first substrate 10. The peripheral region 14 corresponds to a frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In the present modification example, the second substrate 20 includes the plurality of pad electrodes 58 in the region opposed to the peripheral region 14 and the third substrate 30 includes the plurality of pad electrodes 64 in the region opposed to the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically coupled to each other by bonding the pad electrodes 58 and 64 to each other. The pad electrodes 58 and 64 are provided in the region opposed to the peripheral region 14.

In this way, the second substrate 20 and the third substrate 30 are electrically coupled to each other by bonding the pad electrodes 58 and 64 to each other in the present modification example. The pad electrodes 58 and 64 are provided in the region opposed to the peripheral region 14. This makes it possible to reduce the possibility of preventing one pixel from having smaller area as compared with a case where the pad electrodes 58 and 64 are bonded to each other in a region opposed to the pixel region 13. Thus, in addition to the effects of the embodiment described above, it is possible to provide the imaging unit 1 having a three-layer structure that does not prevent one pixel from having smaller area while maintaining a chip size equivalent to an existing chip size.

2-3. Modification Example 3

FIG. 24 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 3) of the embodiment described above in the vertical direction. FIG. 25 illustrates another example of the cross-sectional configuration of the imaging unit (the imaging unit 1) according to the modification example (the modification example 3) of the embodiment described above in the vertical direction. The diagram on the upper side of each of FIGS. 24 and 25 is a modification example of the cross-sectional configuration taken along the cross section Sec1 in FIG. 1 and the diagram on the lower side of FIG. 24 is a modification example of the cross-sectional configuration taken along the cross section Sec2 in FIG. 1. It is to be noted that a diagram illustrating a modification example of the front surface configuration of the semiconductor substrate 11 in FIG. 1 is superimposed on a diagram illustrating the modification example of the cross-sectional configuration taken along the cross section Sec1 in FIG. 1 and the insulating layer 46 is omitted in the cross-sectional view on the upper side of each of FIGS. 24 and 25. In addition, a diagram illustrating a modification example of the front surface configuration of the semiconductor substrate 21 is superimposed on a diagram illustrating the modification example of the cross-sectional configuration taken along the cross section Sec2 in FIG. 1 in the cross-sectional view on the lower side of each of FIGS. 24 and 25.

As illustrated in FIGS. 24 and 25, the plurality of through wiring lines 54, the plurality of through wiring lines 48, and the plurality of through wiring lines 47 (a plurality of dots disposed in a matrix in the diagram) are disposed side by side in a strip shape in the first direction V (the left/right direction in FIGS. 24 and 25) within the plane of the first substrate 10. It is to be noted that each of FIGS. 24 and 25 exemplifies a case where the plurality of through wiring lines 54, the plurality of through wiring lines 48, and the plurality of through wiring lines 47 are disposed side by side in two rows in the first direction V. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are disposed close to each other, for example, with the element separation section 43 interposed in between. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, and TG4) are disposed to surround the four floating diffusions FD and the four transfer gates TG form, for example, an annular shape.

The insulating layer 53 includes a plurality of blocks extending in the first direction V. The semiconductor substrate 21 extends in the first direction V and includes the plurality of island-shaped blocks 21A disposed side by side in the second direction H orthogonal to the first direction V with the insulating layer 53 interposed in between. Each of the blocks 21A is provided, for example, with the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL. The one readout circuit 22 that is shared by the four sensor pixels 12 is not disposed, for example, to be squarely opposed to the four sensor pixels 12, but disposed to shift in the second direction H.

In FIG. 24, the one readout circuit 22 shared by the four sensor pixels 12 includes the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL in a region obtained by shifting, in the second direction H, the region opposed to the four sensor pixels 12 on the second substrate 20. The one readout circuit 22 shared by the four sensor pixels 12 includes, for example, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL in in the one block 21A.

In FIG. 25, the one readout circuit 22 shared by the four sensor pixels 12 includes the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the FD transfer transistor FDG in a region obtained by shifting, in the second direction H, the region opposed to the four sensor pixels 12 on the second substrate 20. The one readout circuit 22 shared by the four sensor pixels 12 includes, for example, the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG in in the one block 21A.

In the present modification example, the one readout circuit 22 that is shared by the four sensor pixels 12 is not disposed, for example, to be squarely opposed to the four sensor pixels 12, but disposed to shift from the position opposed squarely opposed to the four sensor pixels 12 in the second direction H. In such a case, it is possible to shorten the wiring line 25 or it is possible to omit the wiring line 25 and cause the source of the amplification transistor AMP and the drain of the selection transistor SEL to include a common impurity region. As a result, it is possible to reduce the size of the readout circuit 22 or increase the size of another component in the readout circuit 22.

2-4. Modification Example 4

FIG. 26 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 4) of the embodiment described above in the horizontal direction. FIG. 26 illustrates a modification example of the cross-sectional configuration in FIG. 14.

In the present modification example, the semiconductor substrate 21 includes the plurality of island-shaped blocks 21A disposed side by side in the first direction V and the second direction H with the insulating layer 53 interposed in between. Each of the blocks 21A is provided, for example, with one set of reset transistor RST, amplification transistor AMP, and selection transistor SEL. In such a case, it is possible to cause the insulating layer 53 to suppress the crosstalk between the readout circuits 22 adjacent to each other, making it possible to suppress image quality degradation due to a decrease in resolution and color mixing on a reproduced image.

2-5. Modification Example 5

FIG. 27 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 5) of the embodiment described above in the horizontal direction. FIG. 27 illustrates a modification example of the cross-sectional configuration in FIG. 26.

In the present modification example, the one readout circuit 22 that is shared by the four sensor pixels 12 is not disposed, for example, to be squarely opposed to the four sensor pixels 12, but disposed to shift in the first direction V. In the present modification example, the semiconductor substrate 21 further includes the plurality of island-shaped blocks 21A disposed side by side in the first direction V and the second direction H with the insulating layer 53 interposed in between as in the modification example 4. Each of the blocks 21A is provided, for example, with one set of reset transistor RST, amplification transistor AMP, and selection transistor SEL. In the present modification example, the plurality of through wiring lines 47 and the plurality of through wiring lines 54 are further disposed even in the second direction H. Specifically, the plurality of through wiring lines 47 is disposed between the four through wiring lines 54 that share the certain readout circuit 22 and the four through wiring lines 54 that share the other readout circuit 22 adjacent to the certain readout circuit 22 in the second direction H. In such a case, it is possible to cause the insulating layer 53 and the through wiring line 47 to suppress the crosstalk between the readout circuits 22 adjacent to each other, making it possible to suppress image quality degradation due to a decrease in resolution and color mixing on a reproduced image.

2-6. Modification Example 6

FIG. 28 illustrates an example of a cross-sectional configuration of an imaging unit (the imaging unit 1) according to a modification example (a modification example 6) of the embodiment described above in the horizontal direction. FIG. 28 illustrates a modification example of the cross-sectional configuration in FIG. 13.

In the present modification example, the first substrate 10 includes the photodiode PD and the transfer transistor TR for each of the sensor pixels 12 and shares the floating diffusion FD between the four sensor pixels 12. Accordingly, in the present modification example, the one through wiring line 54 is provided for every four sensor pixels 12.

In the plurality of sensor pixels 12 disposed in a matrix, the four sensor pixels 12 corresponding to a region obtained by shifting the unit region corresponding to the four sensor pixels 12 that share the one floating diffusion FD by the one sensor pixel 12 in the first direction V is referred to as four sensor pixels 12A for the sake of convenience. In this case, in the present modification example, the first substrate 10 shares the through wiring line 47 between the four sensor pixels 12A. Accordingly, in the present modification example, the one through wiring line 47 is provided for every four sensor pixels 12A.

In the present modification example, the first substrate 10 includes the element separation section 43 that separates the photodiodes PD and the transfer transistors TR for the respective sensor pixels 12. As viewed from the normal direction of the semiconductor substrate 11, the element separation section 43 does not completely surround the sensor pixel 12. The element separation section 43 has a gap (an unformed region) near the floating diffusion FD (the through wiring line 54) and near the through wiring line 47. The gap then allows the four sensor pixels 12 to share the one through wiring line 54 and allows the four sensor pixels 12A to share the one through wiring line 47. In the present modification example, the second substrate 20 includes the readout circuit 22 for every four sensor pixels 12. The four sensor pixels 12 share the floating diffusion FD.

FIG. 29 illustrates another example of the cross-sectional configuration of the imaging unit 1 according to the present modification example in the horizontal direction. FIG. 29 illustrates a modification example of the cross-sectional configuration in FIG. 26. In the present modification example, the first substrate 10 includes the photodiode PD and the transfer transistor TR for each of the sensor pixels 12 and shares the floating diffusion FD between the four sensor pixels 12. Further, the first substrate 10 includes the element separation section 43 that separates the photodiodes PD and the transfer transistors TR for the respective sensor pixels 12.

FIG. 30 illustrates another example of the cross-sectional configuration of the imaging unit 1 according to the present modification example in the horizontal direction. FIG. 30 illustrates a modification example of the cross-sectional configuration in FIG. 27. In the present modification example, the first substrate 10 includes the photodiode PD and the transfer transistor TR for each of the sensor pixels 12 and shares the floating diffusion FD between the four sensor pixels 12. Further, the first substrate 10 includes the element separation section 43 that separates the photodiodes PD and the transfer transistors TR for the respective sensor pixels 12.

2-7. Modification Example 7

FIG. 31 illustrates an example of a circuit configuration of an imaging unit (e.g., the imaging unit 1) according to a modification example (a modification example 7) of any of the embodiment described above and the modification examples 1 to 6. The imaging unit 1 according to the present modification example is a CMOS image sensor mounted with column-parallel ADC.

As illustrated in FIG. 31, the imaging unit 1 according to the present modification example includes the vertical drive circuit 33, the column signal processing circuit 34, a reference voltage supply section 38, the horizontal drive circuit 35, a horizontal output line 37, and the system control circuit 36 in addition to the pixel region 13 in which the plurality of sensor pixels 12 is two-dimensionally disposed in a matrix (a matrix shape). Each of the plurality of sensor pixels 12 includes a photoelectric conversion element.

In this system configuration, on the basis of a master clock MCK, the system control circuit 36 generates a clock signal, a control signal, or the like that serves as a criterion for an operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, and the like, and provides the clock signal, the control signal, or the like to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, and the like.

In addition, the vertical drive circuit 33 is formed on the first substrate 10 along with each of the sensor pixels 12 of the pixel region 13 and is further formed even on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply section 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 are formed on the third substrate 30.

It is possible to use, as the sensor pixel 12, for example, a component including, in addition to the photodiode PD, the transfer transistor TR that transfers electric charge obtained by photoelectric conversion by the photodiode PD to the floating diffusion FD, although not illustrated here. In addition, it is possible to use, as the readout circuit 22, for example, a component having a three-transistor configuration in which the reset transistor RST that controls the electric potential of the floating diffusion FD, the amplification transistor AMP that outputs a signal corresponding to the electric potential of the floating diffusion FD, and the selection transistor SEL for selecting a pixel are included, although not illustrated here.

In the pixel region 13, the sensor pixels 12 are two-dimensionally disposed. With respect to this m-row and n-column pixel disposition, the pixel drive lines 23 are wired for the respective rows and the vertical signal lines 24 are wired for the respective columns. One end of each of the plurality of pixel drive lines 23 is coupled to a corresponding output end of the rows of the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register or the like and controls the row address and the row scanning of the pixel region 13 through the plurality of pixel drive lines 23.

The column signal processing circuit 34 includes, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for the respective pixel columns or for the respective vertical signal lines 24 of the pixel region 13. The column signal processing circuit 34 converts analog signals outputted column by column from the respective sensor pixels 12 of the pixel region 13 into digital signals and outputs the digital signals.

The reference voltage supply section 38 includes, for example, DAC (digital-to-analog conversion circuit) 38A as a means for generating a reference voltage Vref of a so-called ramp (RAMP) waveform having a level that changes in an inclined manner as time elapses. It is to be noted that the means for generating the reference voltage Vref of the ramp waveform is not limited to the DAC 38A.

Under the control of a control signal CS1 provided from the system control circuit 36, the DAC 38A generates the reference voltage Vref of the ramp waveform on the basis of a clock CK provided from the system control circuit 36 and supplies the generated reference voltage Vref to each of the ADCs 34-1 to 34-m of the column signal processing circuit 34.

It is to be noted that each of the ADCs 34-1 to 34-m is configured to selectively perform an AD conversion operation corresponding to each operation mode of a normal frame rate mode in a progressive scanning system for reading information on all of the sensor pixels 12 and a high-speed frame rate mode for setting exposure time of the sensor pixel 12 to 1/N to increase a frame rate by N times, for example, by twice, as compared with the time of the normal frame rate mode. This switching between the operation modes is executed on the basis of control performed by control signals CS2 and CS3 provided from the system control circuit 36. In addition, instruction information for switching the respective operation modes of the normal frame rate mode and the high-speed frame rate mode is provided from an external system controller (not illustrated) to the system control circuit 36.

All of the ADCs 34-1 to 34-m have the same configuration. The ADC 34-m is described here as an example. The ADC 34-m includes a comparator 34A, an up/down counter (referred to as U/D CNT in the diagram) 34B that is, for example, a number counting means, a transfer switch 34C, and a memory 34D.

The comparator 34A compares a signal voltage Vx of the vertical signal line 24 corresponding to a signal outputted from each of the sensor pixels 12 in an n-th column of the pixel region 13 and the reference voltage Vref of the ramp waveform supplied from the reference voltage supply section 38. For example, in a case where the reference voltage Vref is larger than the signal voltage Vx, an output Vco enters an “H” level. In a case where the reference voltage Vref is the signal voltage Vx or less, the output Vco enters an “L” level.

An up/down counter 34B is an asynchronous counter. Under the control of the control signal CS2 provided from the system control circuit 36, the up/down counter 34B is provided with the clock CK from the system control circuit 36 concurrently with DAC 18A. The up/down counter 34B performs down (DOWN)-counting or up (UP)-counting in synchronization with the clock CK, thereby measuring a comparison period from the start of a comparison operation to the end of the comparison operation in the comparator 34A.

Specifically, in a reading operation of signals from the one sensor pixel 12, the down-counting is performed in the normal frame rate mode upon a first reading operation, thereby measuring comparison time upon the first reading. The up-counting is performed upon a second reading operation, thereby measuring comparison time upon the second reading.

Meanwhile, while holding a count result for the sensor pixel 12 in a certain row as it is in the high-speed frame rate mode, the down-counting is subsequently performed for the sensor pixel 12 in the next row upon a first reading operation from the previous count result, thereby measuring comparison time upon the first reading. The up-counting is performed upon a second reading operation, thereby measuring comparison time upon the second reading.

Under the control by the control signal CS3 provided from the system control circuit 36, the transfer switch 34C is turned on (closed) in the normal frame rate mode upon completion of the counting operation of the up/down counter 34B for the sensor pixel 12 in a certain row and transfers the count results of the up/down counter 34B to the memory 34D.

Meanwhile, for example, in the high-speed frame rate of N=2, the transfer switch 34C remains off (open) upon completion of the counting operation of the up/down counter 34B for the sensor pixel 12 in a certain row and is subsequently turned on upon completion of the counting operation of the up/down counter 34B for the sensor pixel 12 in the next row. The transfer switch 34C transfers the count results of the up/down counter 34B for the vertical two pixels to the memory 34D.

In this way, analog signals supplied for respective columns from the respective sensor pixels 12 of the pixel region 13 through the vertical signal lines 24 are converted into N-bit digital signals by respective operations of the comparators 34A and the up/down counters 34B in the ADCs 34-1 to 34-m and are stored in the memories 34D.

The horizontal drive circuit 35 includes a shift register or the like and controls the column address and the column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals subjected to the AD conversion in the respective ADCs 34-1 to 34-m are read out to the horizontal output line 37 in order and outputted as imaging data through the horizontal output line 37.

It is to be noted that it is also possible to provide, in addition to the components described above, a circuit or the like that performs various kinds of signal processing on the imaging data outputted through the horizontal output line 37, although not illustrated in particular because there is no direct relationship with the present disclosure.

It is possible in the imaging unit 1 mounted with the column-parallel ADC according to the present modification example having the configuration described above to selectively transfer the count results of the up/down counter 34B to the memory 34D through the transfer switch 34C. This makes it possible to independently control the counting operation of the up/down counter 34B and the reading operation of the count results of the up/down counter 34B to the horizontal output line 37.

2-8. Modification Example 8

FIG. 32 illustrates an example in which the imaging unit in FIG. 31 includes three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) that are stacked. In the present modification example, the pixel region 13 is formed in a middle portion of the first substrate 10. the vertical drive circuit 33 is formed around the pixel region 13. The pixel region 13 includes the plurality of sensor pixels 12 is formed. In addition, a readout circuit region 15 is formed in a middle portion of the second substrate 20. The vertical drive circuit 33 is formed around the readout circuit region 15. The readout circuit region 15 includes the plurality of readout circuits 22. In the third substrate 30, the column signal processing circuit 34, the horizontal drive circuit 35, the system control circuit 36, the horizontal output line 37, and the reference voltage supply section 38 are formed. This eliminates an increase in chip size and eliminates the prevention of one pixel from having smaller area due to the structure of electrically coupling substrates to each other as in the embodiment described above and the modification examples thereof. As a result, it is possible to provide the imaging unit 1 having a three-layer structure that does not prevent one pixel from having smaller area while maintaining a chip size equivalent to an existing chip size. It is to be noted that the vertical drive circuit 33 may be formed on the first substrate 10 alone or may be formed on the second substrate 20 alone.

2-9. Modification Example 9

FIG. 33 illustrates an example of a cross-sectional configuration of an imaging unit (e.g., the imaging unit 1) according to a modification example (a modification example 9) of any of the embodiment described above and the modification examples 1 to 8 thereof. In the embodiment described above, the modification examples 1 to 8 thereof, and the like, the imaging unit 1 includes three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) that are stacked. However, as with the imaging units 5 and 6 according to the fifth embodiment described above, an imaging unit may include two substrates (the first substrate 10 and the second substrate 20) that are stacked. In this case, the logic circuit 32 may be formed separately on the first substrate 10 and the second substrate 20, for example, as illustrated in FIG. 33. Here, a circuit 32A of the logic circuit 32 is provided with a transistor having a gate structure in which a high dielectric constant film including a material (e.g., high-k) that is able to withstand a high temperature process and a metal gate electrode are stacked. The circuit 32A is provided on the first substrate 10 side. Meanwhile, in a circuit 32B provided on the second substrate 20 side, for example, a low resistance region 26 that includes a silicide and is formed by using Salicide (Self Aligned Silicide) process such as CoSi₂ and NiSi is formed on the surface of an impurity diffusion region in contact with a source electrode and a drain electrode. The low resistance region including a silicide is formed by using a compound of a material of a semiconductor substrate and metal. This makes it possible to use a high temperature process such as thermal oxidation in a case where the sensor pixel 12 is formed. In addition, it is possible to reduce contact resistance in a case where the low resistance region 26 including a silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the circuit 32B of the logic circuit 32. The circuit 32B is provided on the second substrate 20 side. As a result, it is possible to increase the speed of an arithmetic operation in the logic circuit 32.

2-10. Modification Example 10

FIG. 34 illustrates a modification example of a cross-sectional configuration of the imaging unit 1 according to a modification example (a modification example 10) of any of the first to fourth embodiments described above and the modification examples 1 to 8 thereof. In the logic circuit 32 on the third substrate 30 according to any of the embodiment described above and the modification examples 1 to 8 thereof, a low resistance region 37 that includes a silicide and is formed by using Salicide (Self Aligned Silicide) process such as CoSi₂ and NiSi may be formed on the surface of an impurity diffusion region in contact with a source electrode and a drain electrode. This makes it possible to use a high temperature process such as thermal oxidation in a case where the sensor pixel 12 is formed. In addition, it is possible to reduce contact resistance in a case where the low resistance region 37 including a silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32. As a result, it is possible to increase the speed of an arithmetic operation in the logic circuit 32.

It is to be noted that the electric conductivity type may be opposite in the embodiment described above and the modification examples 1 to 10 thereof. For example, in the descriptions of the embodiment described above and the modification examples 1 to 10 thereof, the p-type may be read as the n-type and the n-type may be read as the p-type. Even in such a case, it is possible to obtain effects similar to those of the first to fifth embodiments described above and the modification examples 1 to 10 thereof.

3. Application Examples

FIG. 35 illustrates an example of a schematic configuration of an imaging system 7 including the imaging unit (the imaging unit 1) according to any of the embodiment described above and the modification examples 1 to 10 thereof.

The imaging system 7 is an electronic apparatus including, for example, an imaging apparatus such as a digital still camera or a video camera, a portable terminal apparatus such as a smartphone or a tablet-type terminal, or the like. The imaging system 7 includes, for example, an optical system 241, a shutter unit 242, the imaging unit 1, a DSP circuit 243, a frame memory 244, a display section 245, a storage section 246, an operation section 247, and a power supply section 248. In the imaging system 7, the shutter unit 242, the imaging unit 1, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, the operation section 247, and the power supply section 248 are coupled to each other through a bus line 249.

The imaging unit 1 outputs image data corresponding to incident light. The optical system 241 includes one or more lenses and guides light (incident light) from a subject to the imaging unit 1 to form an image on a light receiving surface of the imaging unit 1. The shutter unit 242 is disposed between the optical system 241 and the imaging unit 1 and controls a period in which the imaging unit 1 is irradiated with light and a period in which light is blocked under the control of the operation section 247. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) outputted from the imaging unit 1. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 in a frame unit. The display section 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel and displays a moving image or a still image captured by the imaging unit 1. The storage section 246 records image data of a moving image or a still image captured by the imaging unit 1 in a recording medium such as a semiconductor memory or a hard disk. The operation section 247 issues an operation instruction for various functions of the imaging system 7 in accordance with an operation by a user. The power supply section 248 appropriately supplies various kinds of power for operation to the imaging unit 1, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, and the operation section 247 that are supply targets.

Next, an imaging procedure in the imaging system 7 is described.

FIG. 36 illustrates an example of a flowchart of an imaging operation in the imaging system 7. A user issues an instruction to start imaging by operating the operation section 247 (step S101). The operation section 247 then transmits an imaging instruction to the imaging unit 1 (step S102). The imaging unit 1 (specifically, the system control circuit 36) executes imaging in a predetermined imaging scheme upon receiving the imaging instruction (step S103).

The imaging unit 1 outputs light (image data) formed on the light receiving surface through the optical system 241 and the shutter unit 242 to the DSP circuit 243. Here, the image data refers to data for all of the pixels of pixel signals generated on the basis of electric charge temporarily held in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing or the like) on the basis of the image data inputted from the imaging unit 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data subjected to the predetermined signal processing and the frame memory 244 causes the storage section 246 to store the image data (step S105). In this way, the imaging in the imaging system 7 is performed.

In the present application example, the imaging unit 1 is applied to the imaging system 7. This allows the imaging unit 1 to be smaller or higher in definition. This makes it possible to provide the small or high-definition imaging system 7.

FIG. 37 is a diagram illustrating an overview of configuration examples of a non-stacked solid-state imaging unit (a solid-state imaging unit 23210) and a stacked solid-state imaging unit (a solid-state imaging unit 23020) to which the technology according to the present disclosure may be applied.

A of FIG. 37 illustrates a schematic configuration example of a non-stacked solid-state imaging unit. As illustrated in A of FIG. 37, a solid-state imaging unit 23010 includes one die (a semiconductor substrate) 23011. This die 23011 is mounted with a pixel region 23012 in which pixels are disposed in an array, a control circuit 23013 that drives the pixels and performs any other various kinds of control, and a logic circuit 23014 for signal processing.

B and C of FIG. 37 each illustrate a schematic configuration example of a stacked solid-state imaging unit. As illustrated in B and C of FIG. 37, in the solid-state imaging unit 23020, the two dies of a sensor die 23021 and a logic die 23024 are stacked and coupled electrically to serve as one semiconductor chip. These sensor die 23021 and logic die 23024 correspond to specific examples of the “first substrate” and the “second substrate” according to the present disclosure.

In B of FIG. 37, the sensor die 23021 is mounted with the pixel region 23012 and the control circuit 23013 and the logic die 23024 is mounted with the logic circuit 23014 including a signal processing circuit that performs signal processing. Further, a sensor die 20321 may also be mounted, for example, with the readout circuit 22 or the like described above.

In C of FIG. 37, the sensor die 23021 is mounted with the pixel region 23012 and the logic die 23024 is mounted with the control circuit 23013 and the logic circuit 23014.

FIG. 38 is a cross-sectional view illustrating a first configuration example of the stacked solid-state imaging unit 23020.

PD (photodiode) that is included in each of pixels serving as the pixel region 23012, FD (floating diffusion), Tr (MOS FET), Tr serving as the control circuit 23013, and the like are formed in the sensor die 23021. Further, a wiring layer 23101 including a wiring line 23110 including a plurality of layers is formed in the sensor die 23021. In this example, the wiring line 23110 includes three layers. It is to be noted that it is possible to include the control circuit 23013 (the Tr serving as the control circuit 23013) in the logic die 23024 in place of the sensor die 23021.

Tr included in the logic circuit 23014 is formed in the logic die 23024. Further, a wiring layer 23161 including a wiring line 23170 including a plurality of layers is formed in the logic die 23024. In this example, the wiring line 23170 includes three layers. In addition, a coupling hole 23171 having an insulating film 23172 formed on the inner wall surface thereof is formed in the logic die 23024. The coupling hole 23171 is filled with an interconnecting conductor 23173 that is coupled to the wiring line 23170 and the like.

The sensor die 23021 and the logic die 23024 are bonded together with the wiring layers 23101 and 23161 thereof opposed to each other. This forms the stacked solid-state imaging unit 23020 in which the sensor die 23021 and the logic die 23024 are stacked. A film 23191 such as a protective film is formed on the surface on which the sensor die 23021 and the logic die 23024 are bonded together.

A coupling hole 23111 is formed in the sensor die 23021. The coupling hole 23111 extends through the sensor die 23021 from the back surface side (the side where light enters the PD) (the upper side) of the sensor die 23021 and reaches the uppermost layer of the wiring line 23170 of the logic die 23024. Further, a coupling hole 23121 is formed in the sensor die 23021. The coupling hole 23121 is close to the coupling hole 23111 and reaches the first layer of the wiring line 23110 from the back surface side of the sensor die 23021. An insulating film 23112 is formed on the inner wall surface of the coupling hole 23111 and an insulating film 23122 is formed on the inner wall surface of the coupling hole 23121. Interconnecting conductors 23113 and 23123 are then respectively embedded in the coupling holes 23111 and 23121. The interconnecting conductor 23113 and the interconnecting conductor 23123 are electrically coupled on the back surface side of the sensor die 23021. This electrically couples the sensor die 23021 and the logic die 23024 through the wiring layer 23101, the coupling hole 23121, the coupling hole 23111, and the wiring layer 23161.

FIG. 39 is a cross-sectional view illustrating a second configuration example of the stacked solid-state imaging unit 23020.

In the second configuration example of the solid-state imaging unit 23020, one coupling hole 23211 that is formed in the sensor die 23021 electrically couples ((the wiring line 23110 of) the wiring layer 23101 of) the sensor die 23021 and ((the wiring line 23170 of) the wiring layer 23161 of) the logic die 23024.

In other words, in FIG. 39, the coupling hole 23211 is formed to extend through the sensor die 23021 from the back surface side of the sensor die 23021 and reach the uppermost layer of the wiring line 23170 of the logic die 23024 and also reach the uppermost layer of the wiring line 23110 of the sensor die 23021. An insulating film 23212 is formed on the inner wall surface of the coupling hole 23211 and an interconnecting conductor 23213 is embedded in the coupling hole 23211. The sensor die 23021 and the logic die 23024 are electrically coupled by the two coupling holes 23111 and 23121 in FIG. 38 described above, but the sensor die 23021 and the logic die 23024 are electrically coupled by the one coupling hole 23211 in FIG. 39.

FIG. 40 is a cross-sectional view illustrating a third configuration example of the stacked solid-state imaging unit 23020.

The solid-state imaging unit 23020 in FIG. 40 is different from the case of FIG. 38 in that the film 23191 such as a protective film is not formed on the surface on which the sensor die 23021 and the logic die 23024 are bonded together. In the case of FIG. 38, the film 23191 such as a protective film is formed on the surface on which the sensor die 23021 and the logic die 23024 are bonded together.

The solid-state imaging unit 23020 in FIG. 40 is formed by stacking the sensor die 23021 and the logic die 23024 to bring the wiring lines 23110 and 23170 into direct contact and applying desired load and heating them to directly bond the wiring lines 23110 and 23170.

FIG. 41 is a cross-sectional view illustrating another configuration example of the stacked solid-state imaging unit to which the technology according to the present disclosure may be applied.

In FIG. 41, a solid-state imaging unit 23401 has a three-layer stacked structure in which the three dies of a sensor die 23411, a logic die 23412, and a memory die 23413 are stacked.

The memory die 23413 includes, for example, a memory circuit that stores data. The data is temporarily necessary in signal processing performed in the logic die 23412.

In FIG. 41, the logic die 23412 and the memory die 23413 are stacked in this order under the sensor die 23411, but it is possible to stack the logic die 23412 and the memory die 23413 in the inverse order under the sensor die 23411. In other words, it is possible to stack the memory die 23413 and the logic die 23412 in this order.

It is to be noted that, in FIG. 41, PD serving as a photoelectric conversion section of a pixel and a source/drain region of pixel Tr are formed in the sensor die 23411.

A gate electrode is formed around the PD with a gate insulating film interposed in between. The gate electrode and the paired source/drain regions form pixel Tr 23421 and pixel Tr 23422.

The pixel Tr 23421 adjacent to the PD is transfer Tr and one of the paired source/drain regions included in the pixel Tr 23421 is FD.

In addition, an interlayer insulating film is formed in the sensor die 23411 and a coupling hole is formed in the interlayer insulating film. An interconnecting conductor 23431 that is coupled to the pixel Tr 23421 and the pixel Tr 23422 is formed in the coupling hole.

Further, a wiring layer 23433 including a wiring line 23432 that is coupled to each of the interconnecting conductors 23431 is formed in the sensor die 23411. The wiring line 23432 includes a plurality of layers.

In addition, an aluminum pad 23434 serving as an electrode for external coupling is formed in the lowermost layer of the wiring layer 23433 in the sensor die 23411. In other words, the aluminum pad 23434 is formed at a position closer to a joint surface 23440 with the logic die 23412 than the wiring line 23432 in the sensor die 23411. The aluminum pad 23434 is used as an end of a wiring line for inputting and outputting signals to and from the outside.

Further, a contact 23441 is formed in the sensor die 23411. The contact 23441 is used for electrical coupling to the logic die 23412. The contact 23441 is coupled to a contact 23451 in the logic die 23412 and is also coupled to an aluminum pad 23442 in the sensor die 23411.

In the sensor die 23411, a pad hole 23443 is then formed to reach the aluminum pad 23442 from the back surface side (the upper side) of the sensor die 23411.

The technology according to the present disclosure is applicable to solid-state imaging units as described above. For example, the wiring line 23110 or the wiring layer 23161 may be provided, for example, with the plurality of pixel drive lines 23 and the plurality of vertical signal lines 24 described above. In that case, the gaps G as illustrated in FIG. 1 are formed between the wiring lines of the plurality of these vertical signal lines 24. This makes it possible to reduce the capacitance between the wiring lines. In addition, suppressing an increase in the capacitance between the wiring lines makes it possible to reduce variations in the wiring capacitance.

4. Practical Application Examples Practical Application Example 1

The technology (the present technology) according to the present disclosure is applicable to a variety of products. For example, the technology according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

FIG. 42 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 42, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound/image output section 12052, and a vehicle-mounted network interface (I/F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

The sound/image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 42, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

FIG. 43 is a diagram depicting an example of the installation position of the imaging section 12031.

In FIG. 43, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, FIG. 43 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

The above has described the example of the mobile body control system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be applied to the imaging section 12031 among the components described above. Specifically, the imaging units 1 according to the embodiment described above and modification examples thereof are each applicable to the imaging section 12031. The application of the technology according to the present disclosure to the imaging section 12031 makes it possible to obtain a high-definition shot image with less noise and it is thus possible to perform highly accurate control using the shot image in the mobile body control system.

Practical Application Example 2

FIG. 44 is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

In FIG. 44, a state is illustrated in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery for a patient 11132 on a patient bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a supporting arm apparatus 11120 which supports the endoscope 11100 thereon, and a cart 11200 on which various apparatus for endoscopic surgery are mounted.

The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.

The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.

An optical system and an image pickup element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU 11201.

The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).

The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.

The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.

An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.

A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity in order to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.

It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head 11102 are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.

Further, the light source apparatus 11203 may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.

Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and/or excitation light suitable for special light observation as described above.

FIG. 45 is a block diagram depicting an example of a functional configuration of the camera head 11102 and the CCU 11201 depicted in FIG. 44.

The camera head 11102 includes a lens unit 11401, an image pickup unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.

The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

The number of image pickup elements which is included by the image pickup unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit 11402 may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pickup unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pickup elements.

Further, the image pickup unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pickup unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.

The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit 11402 can be adjusted suitably.

The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pickup unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and/or information that a magnification and a focal point of a picked up image are designated.

It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.

The camera head controlling unit 11405 controls driving of the camera head 11102 on the basis of a control signal from the CCU 11201 received through the communication unit 11404.

The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.

Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.

The image processing unit 11412 performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head 11102.

The control unit 11413 performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope 11100 and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.

Further, the control unit 11413 controls, on the basis of an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit 11413 may cause, when it controls the display apparatus 11202 to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.

The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.

Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

The above has described the example of the endoscopic surgery system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be favorably applied to the image pickup unit 11402 provided to the camera head 11102 of the endoscope 11100 among the components described above. The application of the technology according to the present disclosure to the image pickup unit 11402 makes it possible to achieve the downsizing or higher definition of the image pickup unit 11402 and it is thus possible to provide the small or high-definition endoscope 11100.

Although the present disclosure has been described above with reference to the embodiment, the modification examples 1 to 10 thereof, the application example thereof, and the practical application examples thereof, the present disclosure is not limited to the embodiment and the like described above. A variety of modifications are possible. For example, in the embodiment or the like described above, the example has been described in which the plurality of pixel drive lines 23 extends in the row direction and the plurality of vertical signal lines extends in the column direction, but the plurality of pixel drive lines 23 and the plurality of vertical signal lines may both extend in the same direction. In addition, the pixel drive lines 23 may extend as appropriate in a different direction such as the vertical direction.

In addition, in the embodiment or the like described above, the present technology has been described by using, as an example, the imaging unit 1 having a three-dimensional structure, but this is not limitative. The present technology is applicable to any three-dimensional stacked semiconductor device subjected to large scale integration (LSI).

It is to be noted that the effects described herein are merely illustrative. The effects according to the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than the effects described herein.

It is to be noted that the present disclosure may also have configurations as follows. According to the present technology having the following configurations, the first insulating layer is provided on the first wiring layer. The first wiring layer includes the plurality of first wiring lines extending in the one direction. The first insulating layer has the gap between the plurality of first wiring lines and has the stack region above the gap. The first insulating film and the second insulating film are stacked in the stack region. The first insulating film and the second insulating film include materials different from each other. This reduces variations in the film thickness of the first insulating layer within the plane. This makes it possible to reduce variations in the wiring capacitance.

(1)

A semiconductor device in which a first wiring layer and a first insulating layer are stacked,

the first wiring layer including a plurality of first wiring lines extending in one direction,

the first insulating layer forming a gap at least partially between the plurality of wiring lines and having, above the gap, a stack region in which a first insulating film and a second insulating film are stacked, the first insulating film and the second insulating film including materials different from each other.

(2)

The semiconductor device according to (1), in which the second insulating film is formed by using a material having a higher polishing rate than a polishing rate of the first insulating film.

(3)

The semiconductor device according to (1) or (2), in which the first insulating film is formed by using a low dielectric constant material having a relative dielectric constant k of 2.9 or less.

(4)

The semiconductor device according to any one of (1) to (3), in which the second insulating film is formed by using silicon oxide (SiO_(x)), SiOC, SiOF or SiON.

(5)

The semiconductor device according to any one of (1) to (4), in which the first insulating layer is provided with a second wiring layer including a plurality of second wiring lines extending in a same direction as a direction of the plurality of first wiring lines provided in the first wiring layer.

(6)

The semiconductor device according to (5), in which at least a portion of the second wiring layer is formed to be embedded in the stack region.

(7)

The semiconductor device according to any one of (1) to (6), in which a second insulating layer is stacked on the first insulating layer, the second insulating layer being formed by using a material as a material of the first insulating film.

(8)

An imaging unit including:

a first substrate including a sensor pixel on a first semiconductor substrate, the sensor pixel performing photoelectric conversion; and

a second substrate including a readout circuit on a second semiconductor substrate and including a multilayer wiring layer stacked on the second semiconductor substrate, the readout circuit outputting a pixel signal based on electric charge outputted from the sensor pixel, the second substrate being stacked on the first substrate, in which

a first wiring layer and a first insulating layer are stacked in the multilayer wiring layer,

-   -   the first wiring layer including a plurality of first wiring         lines extending in one direction,

the first insulating layer forming a gap at least partially between the plurality of wiring lines and having, above the gap, a stack region in which a first insulating film and a second insulating film are stacked, the first insulating film and the second insulating film including materials different from each other.

(9)

The imaging unit according to (8), in which the second substrate further includes a logic circuit that processes the pixel signal.

(10)

The imaging unit according to (8) or (9), further including a third substrate including at least one of a logic circuit or a memory circuit on a third semiconductor substrate, the logic circuit processing the pixel signal, the memory circuit holding the pixel signal, in which

the first substrate, the second substrate, and the third substrate are stacked in this order.

(11)

The imaging unit according to (10), in which, in a case where the second substrate and the third substrate each include a pad electrode, the second substrate and the third substrate are electrically coupled to each other by bonding the pad electrodes and, in a case where the third substrate includes a second through wiring line that penetrates the third semiconductor substrate, the second substrate and the third substrate are electrically coupled to each other by the second through wiring line.

(12)

The imaging unit according to (11), in which

the sensor pixel includes a photoelectric conversion element, a transfer transistor, and a floating diffusion, the transfer transistor being electrically coupled to the photoelectric conversion element, the floating diffusion temporarily holding electric charge outputted from the photoelectric conversion element through the transfer transistor, and

the readout circuit includes a reset transistor, an amplification transistor, and a selection transistor, the reset transistor resetting an electric potential of the floating diffusion to a predetermined electric potential, the amplification transistor generating, as the pixel signal, a signal of a voltage corresponding to a level of the electric charge held in the floating diffusion, the selection transistor controlling a timing of outputting the pixel signal from the amplification transistor.

(13)

The imaging unit according to (12), in which

the first substrate has a configuration in which the photoelectric conversion element, the transfer transistor, and the floating diffusion are provided on one surface side of the first semiconductor substrate opposed to the second substrate, and

the second substrate has a configuration in which the readout circuit is provided on one surface side of the second semiconductor substrate, the second substrate being bonded to the first substrate with another surface opposed to the one surface side of the first semiconductor substrate, the other surface being opposed to the one surface of the second semiconductor substrate.

(14)

The imaging unit according to (13), in which the third substrate has a configuration in which the logic circuit is provided on one surface side of the third semiconductor substrate, the third substrate being bonded to the second substrate with another surface opposed to the one surface side of the second semiconductor substrate, the other surface being opposed to the one surface of the third semiconductor substrate.

(15)

The imaging unit according to (14), in which the logic circuit includes a silicide on a surface of an impurity diffusion region in contact with a source electrode or a drain electrode.

(16)

The imaging unit according to (14) or (15), in which

a stacked body including the first substrate and the second substrate includes an interlayer insulating film and a first through wiring line between the first semiconductor substrate and the second semiconductor substrate, the first through wiring line being provided in the interlayer insulating film, and

a gate of the transfer transistor is electrically coupled to the logic circuit through the first through wiring line and the pad electrode or the second through wiring line.

(17)

The imaging unit according to any one of (14) to (16), including an interlayer insulating film between the first semiconductor substrate and the second semiconductor substrate, in which

the first substrate further includes a gate wiring line in the interlayer insulating film, the gate wiring line extending in a direction parallel with the first substrate, and

a gate of the transfer transistor is electrically coupled to the logic circuit through the gate wiring line.

(18)

The imaging unit according to (16) or (17), in which

the second substrate includes the readout circuit for every four sensor pixels, and

a plurality of the first through wiring lines is disposed side by side in a strip shape in a first direction within a plane of the first substrate.

(19)

The imaging unit according to (18), in which

the sensor pixels are disposed in a matrix in the first direction and a second direction orthogonal to the first direction, and

the second substrate further includes

-   -   a first control line that is electrically coupled to the gate of         the transfer transistor of each of the sensor pixels disposed         side by side in the second direction,     -   a second control line that is electrically coupled to a gate of         each of the reset transistors disposed side by side in the         second direction,     -   a third control line that is electrically coupled to a gate of         each of the selection transistors disposed side by side in the         second direction, and     -   an output line that is electrically coupled to an output end of         each of the readout circuits disposed side by side in the first         direction.         (20)

The imaging unit according to any one of (8) to (19), in which

the second substrate further includes a plurality of pixel drive lines extending in the one direction and a plurality of vertical signal lines extending in a vertical direction of the plurality of pixel drive lines, and

the gap is provided at least partially between wiring lines of the plurality of vertical signal lines.

(21)

An imaging unit including:

a first substrate including a first semiconductor substrate and a first multilayer wiring layer, the first semiconductor substrate including a sensor pixel and a readout circuit, the sensor pixel performing photoelectric conversion, the readout circuit outputting a pixel signal based on electric charge outputted from the sensor pixel, the first multilayer wiring layer being stacked on the first semiconductor substrate; and

a second substrate including a second semiconductor substrate and a second multilayer wiring layer, the second semiconductor substrate including at least one of a logic circuit or a memory circuit, the logic circuit processing the pixel signal, the memory circuit holding the pixel signal, the second multilayer wiring layer being stacked on the second semiconductor substrate, in which

a first wiring layer and a first insulating layer are stacked in at least one of the first multilayer wiring layer or the second multilayer wiring layer,

-   -   the first wiring layer including a plurality of first wiring         lines extending in one direction,     -   the first insulating layer forming a gap at least partially         between the plurality of wiring lines and having, above the gap,         a stack region in which a first insulating film and a second         insulating film are stacked, the first insulating film and the         second insulating film including materials different from each         other.         (22)

The imaging unit according to (21), in which

the first substrate further includes a plurality of pixel drive lines extending in the one direction and a plurality of vertical signal lines extending in a vertical direction of the plurality of pixel drive lines, and

the gap is provided at least partially between wiring lines of the plurality of vertical signal lines.

This application claims the priority on the basis of Japanese Patent Application No. 2019-041133 filed with Japan Patent Office on Mar. 7, 2019, the entire contents of which are incorporated in this application by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof. 

1. A semiconductor device in which a first wiring layer and a first insulating layer are stacked, the first wiring layer including a plurality of first wiring lines extending in one direction, the first insulating layer forming a gap at least partially between the plurality of wiring lines and having, above the gap, a stack region in which a first insulating film and a second insulating film are stacked, the first insulating film and the second insulating film including materials different from each other.
 2. The semiconductor device according to claim 1, wherein the second insulating film is formed by using a material having a higher polishing rate than a polishing rate of the first insulating film.
 3. The semiconductor device according to claim 1, wherein the first insulating film is formed by using a low dielectric constant material having a relative dielectric constant k of 2.9 or less.
 4. The semiconductor device according to claim 1, wherein the second insulating film is formed by using silicon oxide (SiO_(x)), SiOC, SiOF or SiON.
 5. The semiconductor device according to claim 1, wherein the first insulating layer is provided with a second wiring layer including a plurality of second wiring lines extending in a same direction as a direction of the plurality of first wiring lines provided in the first wiring layer.
 6. The semiconductor device according to claim 5, wherein at least a portion of the second wiring layer is formed to be embedded in the stack region.
 7. The semiconductor device according to claim 1, wherein a second insulating layer is stacked on the first insulating layer, the second insulating layer being formed by using a material as a material of the first insulating film.
 8. An imaging unit comprising: a first substrate including a sensor pixel on a first semiconductor substrate, the sensor pixel performing photoelectric conversion; and a second substrate including a readout circuit on a second semiconductor substrate and including a multilayer wiring layer stacked on the second semiconductor substrate, the readout circuit outputting a pixel signal based on electric charge outputted from the sensor pixel, the second substrate being stacked on the first substrate, wherein a first wiring layer and a first insulating layer are stacked in the multilayer wiring layer, the first wiring layer including a plurality of first wiring lines extending in one direction, the first insulating layer forming a gap at least partially between the plurality of wiring lines and having, above the gap, a stack region in which a first insulating film and a second insulating film are stacked, the first insulating film and the second insulating film including materials different from each other.
 9. The imaging unit according to claim 8, wherein the second substrate further includes a logic circuit that processes the pixel signal.
 10. The imaging unit according to claim 8, further comprising a third substrate including at least one of a logic circuit or a memory circuit on a third semiconductor substrate, the logic circuit processing the pixel signal, the memory circuit holding the pixel signal, wherein the first substrate, the second substrate, and the third substrate are stacked in this order.
 11. The imaging unit according to claim 10, wherein, in a case where the second substrate and the third substrate each include a pad electrode, the second substrate and the third substrate are electrically coupled to each other by bonding the pad electrodes and, in a case where the third substrate includes a second through wiring line that penetrates the third semiconductor substrate, the second substrate and the third substrate are electrically coupled to each other by the second through wiring line.
 12. The imaging unit according to claim 11, wherein the sensor pixel includes a photoelectric conversion element, a transfer transistor, and a floating diffusion, the transfer transistor being electrically coupled to the photoelectric conversion element, the floating diffusion temporarily holding electric charge outputted from the photoelectric conversion element through the transfer transistor, and the readout circuit includes a reset transistor, an amplification transistor, and a selection transistor, the reset transistor resetting an electric potential of the floating diffusion to a predetermined electric potential, the amplification transistor generating, as the pixel signal, a signal of a voltage corresponding to a level of the electric charge held in the floating diffusion, the selection transistor controlling a timing of outputting the pixel signal from the amplification transistor.
 13. The imaging unit according to claim 12, wherein the first substrate has a configuration in which the photoelectric conversion element, the transfer transistor, and the floating diffusion are provided on one surface side of the first semiconductor substrate opposed to the second substrate, and the second substrate has a configuration in which the readout circuit is provided on one surface side of the second semiconductor substrate, the second substrate being bonded to the first substrate with another surface opposed to the one surface side of the first semiconductor substrate, the other surface being opposed to the one surface of the second semiconductor substrate.
 14. The imaging unit according to claim 13, wherein the third substrate has a configuration in which the logic circuit is provided on one surface side of the third semiconductor substrate, the third substrate being bonded to the second substrate with another surface opposed to the one surface side of the second semiconductor substrate, the other surface being opposed to the one surface of the third semiconductor substrate.
 15. The imaging unit according to claim 14, wherein a stacked body including the first substrate and the second substrate includes an interlayer insulating film and a first through wiring line between the first semiconductor substrate and the second semiconductor substrate, the first through wiring line being provided in the interlayer insulating film, and a gate of the transfer transistor is electrically coupled to the logic circuit through the first through wiring line and the pad electrode or the second through wiring line.
 16. The imaging unit according to claim 14, comprising an interlayer insulating film between the first semiconductor substrate and the second semiconductor substrate, wherein the first substrate further includes a gate wiring line in the interlayer insulating film, the gate wiring line extending in a direction parallel with the first substrate, and a gate of the transfer transistor is electrically coupled to the logic circuit through the gate wiring line.
 17. The imaging unit according to claim 8, wherein the second substrate further includes a plurality of pixel drive lines extending in the one direction and a plurality of vertical signal lines extending in a vertical direction of the plurality of pixel drive lines, and the gap is provided at least partially between wiring lines of the plurality of vertical signal lines.
 18. An imaging unit comprising: a first substrate including a first semiconductor substrate and a first multilayer wiring layer, the first semiconductor substrate including a sensor pixel and a readout circuit, the sensor pixel performing photoelectric conversion, the readout circuit outputting a pixel signal based on electric charge outputted from the sensor pixel, the first multilayer wiring layer being stacked on the first semiconductor substrate; and a second substrate including a second semiconductor substrate and a second multilayer wiring layer, the second semiconductor substrate including at least one of a logic circuit or a memory circuit, the logic circuit processing the pixel signal, the memory circuit holding the pixel signal, the second multilayer wiring layer being stacked on the second semiconductor substrate, wherein a first wiring layer and a first insulating layer are stacked in at least one of the first multilayer wiring layer or the second multilayer wiring layer, the first wiring layer including a plurality of first wiring lines extending in one direction, the first insulating layer forming a gap at least partially between the plurality of wiring lines and having, above the gap, a stack region in which a first insulating film and a second insulating film are stacked, the first insulating film and the second insulating film including materials different from each other.
 19. The imaging unit according to claim 18, wherein the first substrate further includes a plurality of pixel drive lines extending in the one direction and a plurality of vertical signal lines extending in a vertical direction of the plurality of pixel drive lines, and the gap is provided at least partially between wiring lines of the plurality of vertical signal lines. 